Datasheet

200
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Figure 78. TWI Bus Topology
A unique address is assigned to all slave devices connected to the bus, and the master will use this to address a slave
and initiate a data transaction. 7-bit or 10-bit addressing can be used.
Several masters can be connected to the same bus, and this is called a multi-master environment. An arbitration
mechanism is provided for resolving bus ownership between masters since only one master device may own the bus at
any given time.
A device can contain both master and slave logic, and can emulate multiple slave devices by responding to more than
one address.
A master indicates the start of transaction by issuing a START condition (S) on the bus. An address packet with a slave
address (ADDRESS) and an indication whether the master wishes to read or write data (R/W
), is then sent. After all data
packets (DATA) are transferred, the master issues a STOP condition (P) on the bus to end the transaction. The receiver
must acknowledge (A) or not-acknowledge (A
) each byte received.
Figure 79 shows a TWI transaction.
Figure 79. Basic TWI Transaction Diagram Topology