Datasheet

20
ATtiny828 [DATASHEET]
8371A–AVR–08/12
5.3.3 Erase
In order to prevent unintentional EEPROM writes, a specific procedure must be followed to erase memory locations. To
erase an EEPROM memory location follow the procedure below:
z Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no other
EEPROM operations are in process. If set, wait to clear.
z Poll the SPMEN bit in Store Program Memory Control and Status Register (SPMCSR) to make sure no self-
programming opertaions are in process. If set, wait to clear. This step is relevant only if the application contains a
boot loader that programs the Flash memory. If not, this step can be omitted.
z Set mode of programming to erase by writing EEPROM Programming Mode bits (EEPM0 and EEPM1) in
EEPROM Control Register (EECR).
z Write target address to EEPROM Address Registers (EEARH/EEARL).
z Enable erase by setting EEPROM Master Program Enable (EEMPE) in EEPROM Control Register (EECR). Within
four clock cycles, start the erase operation by setting the EEPROM Program Enable bit (EEPE) in the EEPROM
Control Register (EECR). During the erase operation, the CPU is halted for two clock cycles before executing the
next instruction.
The EEPE bit remains set until the erase operation has completed. While the device is busy programming, it is not
possible to perform any other EEPROM operations.
5.3.4 Write
In order to prevent unintentional EEPROM writes, a specific procedure must be followed to write to memory locations.
Before writing data to EEPROM the target location must be erased. This can be done either in the same operation or as
part of a split operation. Writing to an unerased EEPROM location will result in corrupted data.
To write an EEPROM memory location follow the procedure below:
z Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no other
EEPROM operations are in process. If set, wait to clear.
z Poll the SPMEN bit in Store Program Memory Control and Status Register (SPMCSR) to make sure no self-
programming opertaions are in process. If set, wait to clear. This step is relevant only if the application contains a
boot loader that programs the Flash memory. If not, this step can be omitted.
z Set mode of programming by writing EEPROM Programming Mode bits (EEPM0 and EEPM1) in EEPROM Control
Register (EECR). Alternatively, data can be written in one operation or the write procedure can be split up in erase,
only, and write, only.
z Write target address to EEPROM Address Registers (EEARH/EEARL).
z Write target data to EEPROM Data Register (EEDR).
z Enable write by setting EEPROM Master Program Enable (EEMPE) in EEPROM Control Register (EECR). Within
four clock cycles, start the write operation by setting the EEPROM Program Enable bit (EEPE) in the EEPROM
Control Register (EECR). During the write operation, the CPU is halted for two clock cycles before executing the
next instruction.
The EEPE bit remains set until the write operation has completed. While the device is busy with programming, it is not
possible to do any other EEPROM operations.
5.3.5 Preventing EEPROM Corruption
During periods of low V
CC
, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and
the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same
design solutions should be applied.