Datasheet

199
ATtiny828 [DATASHEET]
8371A–AVR–08/12
19. I
2
C Compatible, Two-Wire Slave Interface
19.1 Features
z I
2
C compatible
z SMBus compatible (with reservations)
z 100kHz and 400kHz support at low system clock frequencies
z Slew-Rate Limited Output Drivers
z Input Filter provides noise suppression
z 7-bit, and General Call Address Recognition in Hardware
z Address mask register for address masking or dual address match
z 10-bit addressing supported
z Optional Software Address Recognition Provides Unlimited Number of Slave Addresses
z Operates in all sleep modes, including Power Down
z Slave Arbitration allows support for SMBus Address Resolve Protocol (ARP)
19.2 Overview
The Two Wire Interface (TWI) is a bi-directional, bus communication interface, which uses only two wires. The TWI is I
2
C
compatible and, with reservations, SMBus compatible (see “Compatibility with SMBus” on page 205).
A device connected to the bus must act as a master or slave.The master initiates a data transaction by addressing a
slave on the bus, and telling whether it wants to transmit or receive data. One bus can have several masters, and an
arbitration process handles priority if two or more masters try to transmit at the same time.
The TWI module in ATtiny828 implements slave functionality, only. Lost arbitration, errors, collisions and clock holds on
the bus are detected in hardware and indicated in separate status flags.
Both 7-bit and general address call recognition is implemented in hardware. 10-bit addressing is also supported. A
dedicated address mask register can act as a second address match register or as a mask register for the slave address
to match on a range of addresses. The slave logic continues to operate in all sleep modes, including Power down. This
enables the slave to wake up from sleep on TWI address match. It is possible to disable the address matching and let
this be handled in software instead. This allows the slave to detect and respond to several addresses. Smart Mode can
be enabled to auto trigger operations and reduce software complexity.
The TWI module includes bus state logic that collects information to detect START and STOP conditions, bus collision
and bus errors. The bus state logic continues to operate in all sleep modes including Power down.
19.3 General TWI Bus Concepts
The Two-Wire Interface (TWI) provides a simple two-wire bi-directional bus consisting of a serial clock line (SCL) and a
serial data line (SDA). The two lines are open collector lines (wired-AND), and pull-up resistors (Rp) are the only external
components needed to drive the bus. The pull-up resistors will provide a high level on the lines when none of the
connected devices are driving the bus. A constant current source can be used as an alternative to the pull-up resistors.
The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus. A device connected to
the bus can be a master or slave, where the master controls the bus and all communication.
Figure 78 illustrates the TWI bus topology.