Datasheet

198
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Bit 1 – UCPHA: Clock Phase
The UCPHA bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCK. See “SPI
Data Modes and Timing” on page 191 for details.
z Bit 0 – UCPOL: Clock Polarity
The UCPOL bit sets the polarity of the XCK clock. The combination of the UCPOL and UCPHA bit settings determine the
timing of the data transfer. See “SPI Data Modes and Timing” on page 191 for details.
18.8.5 UBRRL and UBRRH – USART MSPIM Baud Rate Registers
The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation. See
“UBRRL and UBRRH – USART Baud Rate Registers” on page 189.