Datasheet

197

ATtiny828 [DATASHEET]

8371A–AVR–08/12

z Bit 4 – RXEN: Receiver Enable

Writing this bit to one enables the USART Receiver in MSPIM mode. The receiver will override normal port operation for

the RxD pin when enabled. Disabling the receiver will flush the receive buffer. Only enabling the receiver in MSPI mode

(i.e. setting RXEN=1 and TXEN=0) has no meaning since it is the transmitter that controls the transfer clock and since

only master mode is supported.

z Bit 3 – TXEN: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The transmitter will override normal port operation for the TxD pin

when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending

transmissions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be

transmitted. When disabled, the transmitter will no longer override the TxD port.

z Bits 2:0 – Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be

written to zero when UCSRB is written.

18.8.4 UCSRC – USART MSPIM Control and Status Register C

z Bits 7:6 – UMSEL[1:0]: USART Mode Select

These bits select the mode of operation of the USART as shown in Table 76. See “UCSRC – USART Control and Status

bits are set to one. The UDORD, UCPHA, and UCPOL can be set in the same write operation where the MSPIM is

enabled.

Table 76. UMSEL Bits Settings

z Bits 5:3 – Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be

written to zero when UCSRC is written.

z Bit 2 – UDORD: Data Order

When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted

first. See “Frame Formats” on page 191 for details.

Bit 7 6 543 2 1 0

(0xC2) UMSEL1 UMSEL0 - - - UDORD UCPHA UCPOL UCSRC

Read/Write R/W R/W R R R R/W R/W R/W

Initial Value 0 0 0 0 0 1 1 0

UMSEL1 UMSEL0 Mode

0 0 Asynchronous USART

0 1 Synchronous USART

1 0 (Reserved)

1 1 Master SPI (MSPIM)