Datasheet

196
ATtiny828 [DATASHEET]
8371A–AVR–08/12
18.8.2 UCSRA – USART MSPIM Control and Status Register A
z Bit 7 – RXC: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e.,
does not contain any unread data). If the receiver is disabled, the receive buffer will be flushed and consequently the
RXC bit will become zero. The RXC flag can be used to generate a Receive Complete interrupt (see RXCIE bit).
z Bit 6 – TXC: USART Transmit Complete
This flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data
currently present in the transmit buffer (UDR). The TXC flag bit is automatically cleared when a transmit complete
interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC flag can generate a Transmit
Complete interrupt (see TXCIE bit).
z Bit 5 – UDRE: USART Data Register Empty
The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty,
and therefore ready to be written. The UDRE flag can generate a Data Register Empty interrupt (see UDRIE bit). UDRE
is set after a reset to indicate that the transmitter is ready.
z Bits 4:0 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be
written to zero when UCSRA is written.
18.8.3 UCSRB – USART MSPIM Control and Status Register n B
z Bit 7 – RXCIE: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if
the RXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set.
z Bit 6 – TXCIE: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if
the TXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC bit in UCSRA is set.
z Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE flag. A Data Register Empty interrupt will be generated only if the
UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA is set.
Bit 7 6 5 4 3 2 1 0
(0xC0) RXC TXC UDRE – – – – – UCSRA
Read/Write R/W R/W R/W R R R R R
Initial Value 0 0 0 0 0 1 1 0
Bit 7 6543210
(0xC1) RXCIE TXCIE UDRIE RXEN TXEN – – – UCSRB
Read/Write R/W R/W R/W R/W R/W R R R
Initial Value 0 0 0 0 0 1 1 0