Datasheet

195
ATtiny828 [DATASHEET]
8371A–AVR–08/12
18.7 AVR USART MSPIM vs. AVR SPI
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
z Master mode timing diagram
z The UCPOL bit functionality is identical to the SPI CPOL bit
z The UCPHA bit functionality is identical to the SPI CPHA bit
z The UDORD bit functionality is identical to the SPI DORD bit
However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is
somewhat different compared to the SPI. In addition to differences of the control register bits, and that only master
operation is supported by the USART in MSPIM mode, the following features differ between the two modules:
z The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer.
z The USART in MSPIM mode receiver includes an additional buffer level.
z The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.
z The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting UBRR
accordingly.
z Interrupt timing is not compatible.
z Pin control differs due to the master only operation of the USART in MSPIM mode.
A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 75.
Table 75. Comparison of USART in MSPIM mode and SPI pins
18.8 Register Description
The following section describes the registers used for SPI operation using the USART.
18.8.1 UDR – USART MSPIM I/O Data Register
The function and bit description of the USART data register (UDR) in MSPI mode is identical to normal USART operation.
See “UDR – USART I/O Data Register” on page 184.
USART_MSPIM SPI Comment
TxD MOSI Master Out only
RxD MISO Master In only
XCK SCK (Functionally identical)
(N/A) SS Not supported by USART in MSPIM