Datasheet

191
ATtiny828 [DATASHEET]
8371A–AVR–08/12
18.4 SPI Data Modes and Timing
There are four combinations of XCK (SCK) phase and polarity with respect to serial data, which are determined by
control bits UCPHA and UCPOL. The data transfer timing diagrams are shown in Figure 77. Data bits are shifted out and
latched in on opposite edges of the XCK signal, ensuring sufficient time for data signals to stabilize. The UCPOL and
UCPHA functionality is summarized in Table 74. Note that changing the setting of any of these bits will corrupt all
ongoing communication for both the receiver and transmitter.
Table 74. UCPOLn and UCPHAn Functionality
Figure 77. UCPHA and UCPOL data transfer timing diagrams.
18.5 Frame Formats
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid
frame formats:
z 8-bit data with MSB first
z 8-bit data with LSB first
A frame starts with the least or most significant data bit. Then follows the next data bits, up to a total of eight, ending with
the most or least significant bit, accordingly. When a complete frame is transmitted, a new frame can directly follow it, or
the communication line can be set to an idle (high) state.
The UDORD bit sets the frame format used by the USART in MSPIM mode. The receiver and transmitter use the same
setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver
and transmitter.
UCPOL UCPHA SPI Mode Leading Edge Trailing Edge
0 0 0 Sample (Rising) Setup (Falling)
0 1 1 Setup (Rising) Sample (Falling)
1 0 2 Sample (Falling) Setup (Rising)
1 1 3 Setup (Falling) Sample (Rising)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
UCPOL=0 UCPOL=1
UCPHA=0
UCPHA=1