Datasheet

190
ATtiny828 [DATASHEET]
8371A–AVR–08/12
18. USART in SPI Mode
18.1 Features
z Full Duplex, Three-wire Synchronous Data Transfer
z Master Operation
z Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
z LSB First or MSB First Data Transfer (Configurable Data Order)
z Queued Operation (Double Buffered)
z High Resolution Baud Rate Generator
z High Speed Operation (fXCKmax = fCK/2)
z Flexible Interrupt Generation
18.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI
compliant mode of operation.
Setting both UMSEL[1:0] bits to one enables the USART in MSPIM logic. In this mode of operation the SPI master
control logic takes direct control over the USART resources. These resources include the transmitter and receiver shift
register and buffers, and the baud rate generator. The parity generator and checker, the data and clock recovery logic,
and the RX and TX control logic is disabled. The USART RX and TX control logic is replaced by a common SPI transfer
control logic. However, the pin control logic and interrupt generation logic is identical in both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the control registers
changes when using MSPIM.
18.3 Clock Generation
The clock generation logic generates the base clock for the transmitter and receiver. For USART MSPIM mode of
operation only internal clock generation (i.e. master operation) is supported. Therefore, for the USART in MSPIM to
operate correctly, the Data Direction Register (DDRx) where the XCK pin is located must be configured to set the pin as
output (DDR_XCK = 1) . Preferably the DDR_XCK should be set up before the USART in MSPIM is enabled (i.e. before
TXEN and RXEN bits are set).
The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The baud rate
or UBRR setting can therefore be calculated using the same equations, see Table 73:
Table 73. Equations for Calculating Baud Rate Register Setting
Note: 1. The baud rate is defined as the transfer rate in bits per second (bps)
BAUD Baud rate (in bits per second, bps)
f
OSC
System oscillator clock frequency
UBRRn Contents of UBRRH and UBRRL, (0-4095)
Operating Mode Calculating Baud Rate
(1)
Calculating UBRR Value
Synchronous Master mode
BAUD
f
OSC
2 UBRR 1+()
-----------------------------------
=
UBRR
f
OSC
2BAUD
--------------------
1–=