Datasheet

186
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Bit 4 – RXEN: Receiver Enable
Writing this bit to one enables the USART Receiver. When enabled, the receiver will override normal port operation for
the RxD pin. Disabling the receiver will flush the receive buffer, invalidating FE, DOR, and UPE Flags.
z Bit 3 – TXEN: Transmitter Enable
Writing this bit to one enables the USART Transmitter. When enabled, the transmitter will override normal port operation
for the TxD pin. Disabling the transmitter (writing TXENn to zero) will not become effective until ongoing and pending
transmissions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be
transmitted. When disabled, the transmitter will no longer override the TxD port.
z Bit 2 – UCSZ2: Character Size
The UCSZ2 bit combined with the UCSZ[1:0] bits sets the number of data bits (Character SiZe) in a frame the receiver
and transmitter use.
z Bit 1 – RXB8: Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. It must be read
before reading the low bits from UDR.
z Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. It must
be written before writing the low bits to UDR.
17.11.4 UCSRC – USART Control and Status Register C
z Bits 7:6 – UMSEL[1:0]: USART Mode Select
These bits select the mode of operation of the USART, as shown in Table 67.
Table 67. USART Mode of Operation
Note: 1. For full description of the Master SPI Mode (MSPIM) Operation, see “USART in SPI Mode” on page 190.
Bit 7 6543210
(0xC2) UMSEL1 UMSEL0 UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
UMSEL1 UMSEL0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 Reserved
1 1 Master SPI (MSPIM)
(1)