Datasheet

185
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Bit 4 – FE: Frame Error
This bit is set if the next character in the receive buffer had a frame error when received (i.e. when the first stop bit of the
next character in the receive buffer is zero). This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when
the stop bit of received data is one.
Always set this bit to zero when writing the register.
z Bit 3 – DOR: Data OverRun
This bit is set if a Data OverRun condition is detected. A data overrun occurs when the receive buffer is full (two
characters), there is a new character waiting in the receive shift register, and a new start bit is detected. This bit is valid
until the receive buffer (UDR) is read.
Always set this bit to zero when writing the register.
z Bit 2 – UPE: USART Parity Error
This bit is set if the next character in the receive buffer had a parity error when received and the parity checking was
enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read.
Always set this bit to zero when writing the register.
z Bit 1 – U2X: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for
asynchronous communication.
z Bit 0 – MPCM: Multi-processor Communication Mode
This bit enables the Multi-processor Communication Mode. When the bit is written to one, all the incoming frames
received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by
the MPCM bit. For more detailed information, see “Multi-processor Communication Mode” on page 180.
17.11.3 UCSRB – USART Control and Status Register B
z Bit 7 – RXCIE: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if
the RXCIE bit, the Global Interrupt Flag, and the RXC bits are set.
z Bit 6 – TXCIE: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if
the TXCIE bit, the Global Interrupt Flag, and the TXC bit are set.
z Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE flag. A Data Register Empty interrupt will be generated only if the
UDRIE bit, the Global Interrupt Flag, and the TXC bit are set.
Bit 76543210
(0xC1) RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 UCSRB
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value00000000