Datasheet

184
ATtiny828 [DATASHEET]
8371A–AVR–08/12
17.11 Register Description
17.11.1 UDR – USART I/O Data Register
The USART transmit data buffer and USART receive data buffer registers share the same I/O address, referred to as
USART Data Register, or UDR. Data written to UDR goes to the Transmit Data Buffer register (TXB). Reading UDR
returns the contents of the Receive Data Buffer register (RXB).
For 5-, 6-, or 7-bit characters the upper, unused bits will be ignored by the transmitter and set to zero by the receiver.
The transmit buffer can only be written when the UDRE flag is set. Data written to UDR when the UDRE flag is not set will
be ignored. When the transmitter is enabled and data is written to the transmit buffer, the transmitter will load the data
into the transmit shift register when it is empty. The data is then serially transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed.
Due to this behavior of the receive buffer, Read-Modify-Write instructions (SBI and CBI) should not be used to access
this location. Care should also be taken when using bit test instructions (SBIC and SBIS), since these also change the
state of the FIFO.
17.11.2 UCSRA – USART Control and Status Register A
z Bit 7 – RXC: USART Receive Complete
This flag is set when there is unread data in the receive buffer, and cleared when the receive buffer is empty (i.e., does
not contain any unread data). If the receiver is disabled, the receive buffer will be flushed and consequently the RXC flag
will become zero. The flag can be used to generate a Receive Complete interrupt (see RXCIE bit).
z Bit 6 – TXC: USART Transmit Complete
This flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data currently
present in the transmit buffer (UDR). The TXC flag bit is automatically cleared when a transmit complete interrupt is
executed, or it can be cleared by writing a one to its bit location. The flag can generate a Transmit Complete interrupt
(see TXCIE bit).
z Bit 5 – UDRE: USART Data Register Empty
The UDRE flag indicates the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and
therefore ready to be written. The UDRE flag can generate a Data Register Empty interrupt (see UDRIE bit).
The UDRE flag is set after a reset to indicate that the transmitter is ready.
Bit 76543210
(0xC6) RXB[7:0] UDR (Read)
(0xC6) TXB[7:0] UDR (Write)
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0xC0) RXC TXC UDRE FE DOR UPE U2X MPCM UCSRA
Read/Write R R/W R R R R R/W R/W
Initial Value00100000