Datasheet

177
ATtiny828 [DATASHEET]
8371A–AVR–08/12
17.8 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock
recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial
frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the
noise immunity of the receiver. The asynchronous reception operational range depends on the accuracy of the internal
baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
17.8.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes the internal clock to the incoming serial frames. Figure 74 illustrates the sampling
process of the start bit of an incoming frame. In normal mode the sample rate is 16 times the baud rate, in double speed
mode eight times. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the double speed mode of operation (U2X = 1). Samples denoted zero are samples
done when the RxD line is idle (i.e., no communication activity).
Figure 74. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection
sequence is initiated. In Figure 74, samples are indicated with numbers inside boxes and sample number 1 denotes the
first zero-sample. The clock recovery logic then uses samples 8, 9, and 10 (in normal mode), or samples 4, 5, and 6 (in
double speed mode), to decide if a valid start bit is received. If two or more of these three samples have logical high
levels (the majority wins), the start bit is rejected as a noise spike and the receiver starts looking for the next high to low-
transition. If, however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can
begin. The synchronization process is repeated for each start bit.
17.8.2 Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a state
machine that has 16 states for each bit in normal mode and eight states for each bit in double speed mode. Figure 75
shows the sampling of the data bits and the parity bit. Each of the samples is given a number that is equal to the state of
the recovery unit.
Figure 75. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples
in the center of the received bit. In the figure, the center samples are emphasized by having the sample number inside
12345678 9 10 11 12 13 14 15 16 12
STARTIDLE
00
BIT 0
3
1234 5 678120
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
12345678 9 10 11 12 13 14 15 16 1
BIT n
1234 5 6781
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)