Datasheet

176
ATtiny828 [DATASHEET]
8371A–AVR–08/12
protocol handling. The flag is not affected by the USBS bit, since the receiver ignores all stop bits, except the first.
For compatibility with future devices, this bit must always be cleared when writing UCSRA.
z The Data OverRun flag (DOR) indicates data loss due to a receiver buffer full condition. A data overrun situation
occurs when the receive buffer is full (two characters), there is a new character waiting in the receive shift register,
and a new start bit is detected. If the flag is set there was one or more serial frames lost between the frame last
and the next frame read from UDR. For compatibility with future devices, this bit must always be cleared when
writing to UCSRA. The flag is cleared when the frame received was successfully moved from the shift register to
the receive buffer.
z The Parity Error flag (UPE) indicates that the next frame in the receive buffer had a parity error. If parity check is
not enabled the flag will always be zero. For compatibility with future devices, this bit must always be cleared when
writing UCSRA. For more details, see “Parity Bit Calculation” on page 168 and “Parity Checker” on page 176.
17.7.5 Parity Checker
The parity checker is active when the high USART Parity Mode bit (UPM1) is set. The type of parity check to be
performed (odd or even) is selected by the UPM0 bit. When enabled, the parity checker calculates the parity of the data
bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored
in the receive buffer together with the received data and stop bits. The Parity Error flag (UPE) can then be read by
software to check if the frame had a parity error.
If parity checking is enabled (UPM = 1), the UPE bit is set if the next character that can be read from the receive buffer
had a parity error when received. This bit is valid until the receive buffer (UDR) is read.
17.7.6 Disabling the Receiver
Unlike the transmitter, the receiver is disabled immediately and any data from ongoing receptions will be lost. When
disabled (RXEN = 0), the receiver will no longer override the normal function of the RxD port pin and the FIFO buffer is
flushed, with any remaining data in the buffer lost.
17.7.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the receiver is disabled, i.e., the buffer will be emptied of its contents.
Unread data will be lost. To flush the buffer during normal operation, due to for instance an error condition, read the UDR
until the RXC flag is cleared. The following code example shows how to flush the receive buffer.
Note: 1. See “Code Examples” on page 7.
Assembly Code Example
(1)
USART_Flush:
sbis UCSRA, RXC
ret
in r16, UDR
rjmp USART_Flush
C Code Example
(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRA & (1<<RXC) ) dummy = UDR;
}