Datasheet

172
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Notes: 1. These transmit functions are written to be general functions. They can be optimized if the contents of the
UCSRB is static. For example, only the TXB8 bit of UCSRB is used after initialization.
2. See “Code Examples” on page 7.
The ninth bit can be used for indicating an address frame when using multi processor communication mode or for other
protocol handling as for example synchronization.
17.6.3 Transmitter Flags and Interrupts
The USART transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and Transmit
Complete (TXC). Both flags can be used for generating interrupts.
The Data Register Empty flag (UDRE) indicates whether the transmit buffer is ready to receive new data. This bit is set
when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet
been moved into the shift register. For compatibility with future devices, always write this bit to zero when writing UCSRA.
When the Data Register Empty Interrupt Enable bit (UDRIE) is set, the USART Data Register Empty Interrupt will be
executed as long as UDRE is set (and provided that global interrupts are enabled). UDRE is cleared by writing UDR.
When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to
UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the
interrupt routine terminates.
The Transmit Complete flag (TXC) is set when the entire frame in the transmit shift register has been shifted out and
there are no new data currently present in the transmit buffer. The TXC flag is automatically cleared when a transmit
complete interrupt is executed, or it can be cleared by writing a one to its location. The TXC flag is useful in half-duplex
communication interfaces (like the RS-485 standard), where a transmitting application must enter receive mode and free
the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable bit (TXCIE) is set, the USART Transmit Complete Interrupt will be
executed when the TXC flag becomes set (and provided that global interrupts are enabled). When the transmit complete
interrupt is used, the interrupt handling routine does not have to clear the TXC flag, since this is done automatically when
the interrupt is executed.
17.6.4 Parity Generator
The parity generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPM1 = 1), the
transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent.
C Code Example
(1)(2)
void USART_Transmit( unsigned int data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRA & (1<<UDRE))) )
;
/* Copy 9th bit to TXB8 */
UCSRB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRB |= (1<<TXB8);
/* Put data into buffer, sends the data */
UDR = data;
}