Datasheet

17
ATtiny828 [DATASHEET]
8371A–AVR–08/12
5.2 Data Memory (SRAM) and Register Files
Table 3 shows how the data memory and register files of ATtiny828 are organized. These memory areas are volatile, i.e.
they do not retain information when power is removed.
Table 3. Layout of Data Memory and Register Area
Note: 1. Also known as data address. This mode of addressing covers the entire data memory and register area. The
address is contained in a 16-bit area of two-word instructions.
2. Also known as direct I/O address. This mode of addressing covers part of the register area, only. It is used
by instructions where the address is embedded in the instruction word.
The 768 memory locations include the general purpose register file, I/O register file, extended I/O register file, and the
internal data memory.
For compatibility with future devices, reserved bits should be written to zero, if accessed. Reserved I/O memory
addresses should never be written.
5.2.1 General Purpose Register File
The first 32 locations are reserved for the general purpose register file. These registers are described in detail in “General
Purpose Register File” on page 9.
5.2.2 I/O Register File
Following the general purpose register file, the next 64 locations are reserved for I/O registers. Registers in this area are
used mainly for communicating with I/O and peripheral units of the device. Data can be transferred between I/O space
and the general purpose register file using instructions such as IN, OUT, LD, ST, and derivatives.
All I/O registers in this area can be accessed with the instructions IN and OUT. These I/O specific instructions address
the first location in the I/O register area as 0x00 and the last as 0x3F.
The low 32 registers (address range 0x00...0x1F) are accessible by some bit-specific instructions. In these registers, bits
are easily set and cleared using SBI and CBI, while bit-conditional branches are readily constructed using instructions
SBIC, SBIS, SBRC, and SBRS.
Registers in this area may also be accessed with instructions LD/LDD/LDI/LDS and ST/STD/STS. These instructions
treat the entire volatile memory as one data space and, therefore, address I/O registers starting at 0x20.
See “Instruction Set Summary” on page 301.
ATtiny828 also contains three general purpose I/O registers that can be used for storing any information. See GPIOR0,
GPIOR1 and GPIOR2 in “Register Summary” on page 297. These general purpose I/O registers are particularly useful
for storing global variables and status flags, since they are accessible to bit-specific instructions such as SBI, CBI, SBIC,
SBIS, SBRC, and SBRS.
Device Memory Area Size Long Address
(1)
Short Address
(2)
ATtiny828
General purpose register file 32B 0x0000 – 0x001F n/a
I/O register file 64B 0x0020 – 0x005F 0x00 – 0x3F
Extended I/O register file 160B 0x0060 – 0x00FF n/a
Data SRAM 512B 0x0100 – 0x02FF n/a