Datasheet
168
ATtiny828 [DATASHEET]
8371A–AVR–08/12
17.4 Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a
parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats:
z Start bit: 1
z Data bits: 5, 6, 7, 8, or 9
z Parity bit: no, even, or odd parity
z Stop bits: 1, or 2
A frame begins with the start bit followed by the least significant data bit. Then follows the other data bits, the last one
being the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a
complete frame has been transmitted it can be directly followed by a new frame, or the communication line can be set to
an idle (high) state.
Figure 73 illustrates the possible combinations of the frame formats. Bits inside brackets are optional.
Figure 73. Frame Formats
Signal description for Figure 73:
St Start bit (always low)
(n) Data bits (0 to 4/5/6/7/8)
P Parity bit, if enabled (odd or even)
Sp Stop bit (always high)
IDLE No transfers on the communication line (RxDn or TxDn). (high)
The frame format used by the USART is set by the UCSZ, UPM and USBS bits (see “UCSRB – USART Control and
Status Register B” on page 185 and “UCSRC – USART Control and Status Register C” on page 186), as follows:
z The USART Character SiZe bits (UCSZ) select the number of data bits in the frame
z The USART Parity Mode bits (UPM) choose the type of parity bit
z The selection between one or two stop bits is done by the USART Stop Bit Select bit (USBS). The receiver ignores
the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero.
The receiver and transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all
ongoing communication for both the receiver and transmitter.
17.4.1 Parity Bit Calculation
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or
is inverted. The relation between the parity bit and data bits is as follows:
... where:
10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)
FRAME
P
EVEN
d
n 1–
… d
3
d
2
d
1
d
0
0⊕⊕⊕⊕⊕⊕=
P
ODD
d
n 1–
… d
3
d
2
d
1
d
0
1⊕⊕⊕⊕⊕⊕=