Datasheet

167
ATtiny828 [DATASHEET]
8371A–AVR–08/12
17.3.2 Double Speed Operation (U2X)
The transfer rate can be doubled by setting the U2X bit ( see “UCSRA – USART MSPIM Control and Status Register A”
on page 196). Setting this bit only has effect in asynchronous mode of operation. In synchronous mode of operation this
bit should be cleared.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for
asynchronous communication. Note, however, that in this case the receiver will use half the number of samples, only. In
double speed mode, the number of data and clock recovery sampels are reduced from 16 to 8, and therefore a more
accurate baud rate setting and system clock are required.
There are no downsides for the transmitter.
17.3.3 External Clock
External clocking is used in synchronous slave modes of operation. To minimize the chance of meta-stability, the
external clock input from the XCK pin is sampled by a synchronization register. The output from the synchronization
register then passes through an edge detector before it is used by the transmitter and receiver. This process introduces
a delay of two CPU clocks, and therefore the maximum external clock frequency is limited by the following equation:
Note that f
osc
depends on the stability of the system clock source. It is therefore recommended to add some margin to
avoid possible data loss due to frequency variations.
17.3.4 Synchronous Clock Operation
In synchronous mode (UMSEL = 1), the XCK is used as either clock input (slave mode) or clock output (master mode).
The dependency between clock edges and data sampling or data change is the same. The basic principle is that data
input (on RxD) is sampled on the opposite XCK clock edge when data output (TxDn) is changed.
Which XCK clock edge is used for data sampling and which is used for data change can be changed with the UCPOL bit
(see “UCSRC – USART MSPIM Control and Status Register C” on page 197).
Figure 72. Synchronous Mode XCK Timing.
As shown in Figure 72, when UCPOL is set, the data is changed at falling XCK edge and sampled at rising XCK edge.
When UCPOL is cleared, the data is changed at rising XCK edge and sampled at falling XCK edge.
f
XCK
f
OSC
4
-----------
<
RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample