Datasheet

166
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Normal asynchronous mode
z Double speed asynchronous mode
z Master synchronous mode
z Slave synchronous mode
The UMSEL bit (see “UCSRC – USART Control and Status Register C” on page 186) selects between asynchronous
and synchronous operation. In asynchronous mode, the speed is controlled by the U2X bit (see “UCSRA – USART
Control and Status Register A” on page 184).
In synchronous mode (UMSEL = 1), the direction bit of the XCK pin (DDR_XCK) in the Data Direction Register where the
XCK pin is located (DDRx) controls whether the clock source is internal (master mode), or external (slave mode). The
XCK pin is active in synchronous mode, only.
17.3.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used in asynchronous and synchronous master modes of operation. The description in this
section refers to Figure 71 on page 165.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler, or
baud rate generator. The down-counter, running at system clock (f
osc
) is loaded with the UBRR value each time the
counter has counted down to zero, or when UBRR0L is written.
A clock is generated each time the counter reaches zero. This is the baud rate generator clock output and has a
frequency of f
osc
/(UBRR+1). Depending on the mode of operation the transmitter divides the baud rate generator clock
output by 2, 8 or 16. The baud rate generator output is used directly by the receiver’s clock and data recovery units.
However, the recovery units use a state machine that uses 2, 8 or 16 states, depending on mode set by UMSEL, U2X
and DDR_XCK bits.
Table 60 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each
mode of operation using an internally generated clock source.
Table 60. Equations for Calculating Baud Rate Register Setting
Note: 1. Baud rate is defined as the transfer rate in bits per second (bps)
Signal description for Table 60:
BAUD Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRR Contents of the UBRRH and UBRRL Registers, (0-4095)
Some examples of UBRR values for selected system clock frequencies are shown in Table 63 on page 181.
Operating Mode Baud Rate
(1)
UBRR Value
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double Speed
mode (U2Xn = 1)
Synchronous Master
mode
BAUD
f
OSC
16 UBRR 1+()×
-------------------------------------------
=
UBRR
f
OSC
16 BAUD×
-----------------------------
1–=
BAUD
f
OSC
8 UBRR 1+()×
----------------------------------------
=
UBRR
f
OSC
8 BAUD×
--------------------------
1–=
BAUD
f
OSC
2 UBRR 1+()×
----------------------------------------
=
UBRR
f
OSC
2 BAUD×
--------------------------
1–=