Datasheet

165
ATtiny828 [DATASHEET]
8371A–AVR–08/12
For USART pin placement, see Figure 1 on page 2 and “Alternative Port Functions” on page 63.
The dashed boxes in the block diagram of Figure 70 illustrate the three main parts of the USART, as follows(listed from
the top):
z Clock generator
z Transmitter
z Receiver
The clock generation logic consists of synchronization logic (for external clock input in synchronous slave operation), and
the baud rate generator. The transfer clock pin (XCK) is only used in synchronous transfer mode.
The transmitter consists of a single write buffer, a serial shift register, a parity generator and control logic for handling
different serial frame formats. The write buffer allows a continuous transfer of data without delay between frames.
The receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units
are used for asynchronous data reception. In addition to the recovery units, the receiver includes a parity checker, control
logic, a ahift register and a two level receive buffer (UDR). The receiver supports the same frame formats as the
transmitter, and can detect the following errors:
z Frame Error
z Data Overrun Error
z Parity Errors.
In order for the USART to be operative the USART power reducion bit must be disabled. See “PRR – Power Reduction
Register” on page 37.
17.3 Clock Generation
The clock generation logic creates the base clock for the transmitter and receiver. A block diagram of the clock
generation logic is shown in Figure 71.
Figure 71. Clock Generation Logic, Block Diagram
Signal description for Figure 71:
txclk Transmitter clock (Internal Signal)
rxclk Receiver base clock (Internal Signal)
xcki Input from XCK pin (internal Signal). Used for synchronous slave operation
xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation
f
OSC
XTAL pin frequency (System Clock)
The USART supports four modes of clock operation, as follows:
Prescaling
Down-Counter
/2
UBRR
/4 /2
fosc
UBRR+1
Sync
Register
OSC
XCK
Pin
txclk
U2X
UMSEL
DDR_XCK
0
1
0
1
xcki
xcko
DDR_XCK
rxclk
0
1
1
0
Edge
Detector
UCPOL