Datasheet

163
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Bits 5:1 – Res: Reserved Bits
These bits are reserved and will always read as zero.
z Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is set the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 59 on
page 162). This means that the minimum SCK period will be two I/O clock periods. When the SPI is configured as Slave,
the SPI is only guaranteed to work at f
clk_I/O
/4 or lower.
16.5.3 SPDR – SPI Data Register
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register.
Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be
read.
Bit 76543210
0x2E (0x4E) MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value XXXXXXXXUndefined