Datasheet

162
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of
SCK. Refer to Figure 68 and Figure 69 for an example. The CPOL functionality is summarized below:
Table 58. CPHA Functionality
z Bits 1:0 – SPR[1:0]: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave.
The relationship between SCK and the I/O clock frequency f
clk_I/O
is shown in the following table:
Table 59. Relationship Between SCK and the I/O Clock Frequency
16.5.2 SPSR – SPI Status Register
z Bit 7 – SPIF: SPI Interrupt Flag
This bit is set when a serial transfer is complete. An interrupt is generated if SPIE in SPCR is set and global interrupts are
enabled. If SS
is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by
first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
z Bit 6 – WCOL: Write COLlision Flag
This bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are
cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.
CPHA Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample
SPI2X SPR1 SPR0 SCK Frequency
0 0 0 f
clk_I/O
/4
0 0 1 f
clk_I/O
/16
0 1 0 f
clk_I/O
/64
0 1 1 f
clk_I/O
/128
1 0 0 f
clk_I/O
/2
1 0 1 f
clk_I/O
/8
1 1 0 f
clk_I/O
/32
1 1 1 f
clk_I/O
/64
Bit 76543210
0x2D (0x4D) SPIF WCOL – – – – – SPI2X SPSR
Read/Write R/W R/W R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0