Datasheet

161
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Table 56. SPI Modes
16.5 Register Description
16.5.1 SPCR – SPI Control Register
z Bit 7 – SPIE: SPI Interrupt Enable
When this bit is set, the SPI interrupt is enabled. Provided the Global Interrupt Enable bit in SREG is set, the SPI interrupt
service routine will be executed when the SPIF bit in SPSR is set.
z Bit 6 – SPE: SPI Enable
When this bit is set, the SPI is enabled. This bit must be set to enable any SPI operations.
z Bit 5 – DORD: Data Order
When this bit is set, the LSB of the data word is transmitted first.
When this bit is cleared, the MSB of the data word is transmitted first.
z Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS
is configured as
an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will
then have to set MSTR to re-enable SPI Master mode.
z Bit 3 – CPOL: Clock Polarity
When this bit is set, SCK is high when idle. When this bit is cleared, SCK is low when idle. Refer to Figure 68 and Figure
69 for an example. The CPOL functionality is summarized below:
Table 57. CPOL Functionality
SPI Mode Conditions Leading Edge Trailing eDge
0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling)
1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling)
2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising)
3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising)
Bit 76543210
0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
CPOL Leading Edge Trailing Edge
0 Rising Falling
1 Falling Rising