Datasheet

153
ATtiny828 [DATASHEET]
8371A–AVR–08/12
15.13.5 ADCSRB – ADC Control and Status Register B
z Bit 5 – Res: Reserved Bit
Thisis a reserved bit. For compatibility with future devices always write this bit to zero.
z Bit 3 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to
left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register
immediately, regardless of any ongoing conversions. For a comple the description of this bit, see “ADCL and ADCH –
ADC Data Register” on page 151.
z Bits 2:0 – ADTS[2:0] : ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If
ADATE is cleared, the ADTS[2:0] settings will have no effect. A conversion will be triggered by the rising edge of the
selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will
generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free
Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
.
Table 54. ADC Auto Trigger Source Selections
Bit 76543210
(0x7B)
– ––– ADLAR ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R R R R/W R/W R/W R/W
Initial Value 00000000
ADTS2 ADTS1 ADTS0 Trigger Source
0 0 0 Free Running mode
0 0 1 Analog Comparator
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare Match A
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter1 Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event