Datasheet

151
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Bit 0 – MUX5: Analog Channel and Gain Selection Bit
This bit together with MUX[4:0] in ADMUXA select which analog input is connected to the ADC. See Table 51 on page
149.
15.13.3 ADCL and ADCH – ADC Data Register
15.13.3.1ADLAR = 0
15.13.3.2ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted
and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then
ADCH.
The ADLAR bit and the MUX bits affect the way the result is read from the registers. If ADLAR is set, the result is left
adjusted. If ADLAR is cleared (default), the result is right adjusted.
z ADC[9:0]: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 148.
15.13.4 ADCSRA – ADC Control and Status Register A
z Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a
conversion is in progress, will terminate this conversion.
Bit 151413121110 9 8
(0x79) ––––––ADC9ADC8ADCH
(0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
76543210
Read/Write RRRRRRRR
RRRRRRRR
Initial Value 00000000
00000000
Bit 151413121110 9 8
(0x79) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
(0x78) ADC1 ADC0 ––––––ADCL
76543210
Read/Write RRRRRRRR
RRRRRRRR
Initial Value 00000000
00000000
Bit 76543210
(0x7A) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0