Datasheet

149
ATtiny828 [DATASHEET]
8371A–AVR–08/12
15.13 Register Description
15.13.1 ADMUXA – ADC Multiplexer Selection Register A
z Bits 4:0 – MUX[4:0] : Analog Channel and Gain Selection Bits
These bits together with MUX5 in ADMUXB select which analog input is connected to the ADC. See Table 51.
Table 51. Single-Ended Input channel Selections
Bit 76543210
(0x7C)
– – – MUX4 MUX3 MUX2 MUX1 MUX0 ADMUXA
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
MUX[5:0] Single Ended Input Pin
000000 ADC0 PA0
000001 ADC1 PA1
000010 ADC2 PA2
000011 ADC3 PA3
000100 ADC4 PA4
000101 ADC5 PA5
000110 ADC6 PA6
000111 ADC7 PA7
001000 ADC8 PB0
001001 ADC9 PB1
001010 ADC10 PB2
001011 ADC11 PB3
001100 ADC12 PB4
001101 ADC13 PB5
001110 ADC14 PB6
001111 ADC15 PB7
010000 ADC16 PC0
010001 ADC17 PC1
010010 ADC18 PC2
010011 ADC19 PC3
010100 ADC20 PC4
010101 ADC21 PC5
010110 ADC22 PC6
010111 ADC23 PC7