Datasheet

144
ATtiny828 [DATASHEET]
8371A–AVR–08/12
15.7 ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode. This reduces noise induced from the
CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make
use of this feature, the following procedure should be used:
z Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the
ADC conversion complete interrupt must be enabled.
z Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.
z If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and
execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC
conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be
generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command
is executed.
Note that the ADC will not automatically be turned off when entering other sleep modes than Idle mode and ADC Noise
Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power
consumption.
15.8 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 60. An analog source applied to ADCn is
subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for
the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined
resistance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10kΩ or less. If such a source is
used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on
how long time the source needs to charge the S/H capacitor, which can vary widely. The user is recommended to only
use low impedance sources with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
In order to avoid distortion from unpredictable signal convolution, signal components higher than the Nyquist frequency
(f
ADC
/2) should not be present. The user is advised to remove high frequency components with a low-pass filter before
applying the signals as inputs to the ADC.
Figure 60. Analog Input Circuitry
Note: The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic
capacitance inside the device. The value given is worst case.
ADCn
I
IH
1..100 kohm
C
S/H
= 14 pF
V
CC
/2
I
IL