Datasheet

143
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Table 49. ADC Conversion Time
15.6 Changing Channel or Reference Selection
The MUX and REFS bits are single buffered through a temporary register to which the CPU has random access. This
ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel
and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel
and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the
last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the
following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference
selection values until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when
updating the ADMUXA and ADMUXB registers, in order to control which conversion will be affected by the new settings.
If both ADATE and ADEN are written to one, an interrupt event can occur at any time. If the ADCSRA register is changed
in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADCSRA can be safely
updated under the following conditions:
z When ADATE or ADEN is cleared.
z During conversion: at least one ADC clock cycle after the trigger event.
z After a conversion: before the Interrupt flag used as trigger source is cleared.
When updating in one of these conditions, the new settings will affect the next ADC conversion.
15.6.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is
selected:
z In Single Conversion mode, always select the channel before starting the conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the
conversion to complete before changing the channel selection.
z In Free Running mode, always select the channel before starting the first conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first
conversion to complete, and then change the channel selection. Since the next conversion has already started
automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the
new channel selection.
15.6.2 ADC Voltage Reference
The ADC reference voltage (V
REF
) indicates the conversion range for the ADC. Single ended channels that exceed V
REF
will result in codes close to 0x3FF. V
REF
can be selected as either V
CC
, or internal 1.1V reference. The internal 1.1V
reference is generated from the internal bandgap reference (V
BG
) through an internal amplifier.
The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to
discard this result.
Condition
Sample & Hold
(Cycles from Start of Conversion)
Conversion Time
(Cycles)
First conversion 15 26
Normal conversions 4 15
Auto Triggered conversions 4.5 15.5
Free Running conversion 4 15