Datasheet

142
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Figure 58. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC
remains high. See Figure 59.
Figure 59. ADC Timing Diagram, Free Running Conversion
For a summary of conversion times, see Table 49 on page 143.
1 2 3 4 5 6 7 8
9
13 14 15
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
13 14 15
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
34
Conversion
Complete
Sample & Hold
MUX and REFS
Update
5