Datasheet

141
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Figure 56. ADC Timing Diagram, First Conversion (Single Conversion Mode)
The actual sample-and-hold takes place 4 ADC clock cycles after the start of a normal conversion and 15 ADC clock
cycles after the start of a first conversion. See Figure 57. When a conversion is complete, the result is written to the ADC
Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then
set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
Figure 57. ADC Timing Diagram, Single Conversion
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 58 below. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place 4.5
ADC clock cycles after the rising edge on the trigger source signal. Two additional CPU clock cycles are used for
synchronization logic.
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1 213
14
15 16
17 18
19 20 21 22 23 24
25 26
1 2
First Conversion
Next
Conversion
3
MUX and REFS
Update
MUX and REFS
Update
Conversion
Complete
1
2 3 4 5 6 7 8
11 12 13 14 15
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update