Datasheet
140
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data
Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC
will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be
used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of
how the conversion was started.
15.5 Prescaling and Conversion Timing
By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get
maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than
200 kHz to get a higher sample rate. It is not recommended to use a higher input clock frequency than 1 MHz.
Figure 55. ADC Prescaler
The ADC module contains a prescaler, as illustrated in Figure 55 on page 140, which generates an acceptable ADC
clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The
prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler
keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following
rising edge of the ADC clock cycle.
A normal conversion takes 15 ADC clock cycles, as summarised in Table 49 on page 143. The first conversion after the
ADC is switched on (ADEN in ADCSRA is set) takes 26 ADC clock cycles in order to initialize the analog circuitry, as
shown in Figure 56 below.
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START