Datasheet

ATtiny828 [DATASHEET]

8371A–AVR–08/12

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter

(two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

4.8 Register Description

4.8.1 CCP – Configuration Change Protection Register

z Bits 7:0 – CCP[7:0]: Configuration Change Protection

In order to change the contents of a protected I/O register the CCP register must first be written with the correct

signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles.

All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again by the CPU,

and any pending interrupts will be executed according to their priority.

When the protected I/O register signature is written, CCP0 will read as one as long as the protected feature is enabled,

while CCP[7:1] will always read as zero.

Table 1 shows the signatures that are recognised.

Table 1. Signatures Recognised by the Configuration Change Protection Register

Notes: 1. Only WDE and WDP[3:0] bits are protected in WDTCSR.

4.8.2 SPH and SPL — Stack Pointer Registers

z Bits 9:0 – SP[9:0]: Stack Pointer

The Stack Pointer register points to the top of the stack, which is implemented growing from higher memory locations to

lower memory locations. Hence, a stack PUSH command decreases the Stack Pointer.

The stack space in the data SRAM must be defined by the program before any subroutine calls are executed or

interrupts are enabled.

Bit 76543210

0x36 (0x56) CCP[7:0] CCP

Read/WriteWWWWWWWR/W

Initial Value00000000

Signature Registers Description

0xD8 CLKPR, MCUCR, WDTCSR

(1)

Protected I/O register

Initial Value

000000RAMENDRAMEND

Read/Write RRRRRRR/WR/W

Bit 151413121110 9 8

0x3E (0x5E)

––––––SP9

SP8 SPH

0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value

RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND