Datasheet

138
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Figure 53. Analog to Digital Converter Block Schematic
15.3 Operation
In order to be able to use the ADC the Power Reduction bit, PRADC, in the Power Reduction Register must be disabled.
This is done by clearing the PRADC bit. See “PRR – Power Reduction Register” on page 37 for more details.
ADMUXAADMUXA
DECODERDECODER
8-BIT DATA BUS
MUX[4:0]
ADCSRAADCSRA
ADCH+ADCLADCH+ADCL
ADPS0
ADEN
ADPS1 ADPS2
ADATE
ADIF
ADSC
TRIGGERTRIGGER
SELECTSELECT
ADTS[2:0]
START
PRESCALERPRESCALER
ADC9:0
CONVERSION LOGICCONVERSION LOGIC
10-BIT DAC10-BIT DAC
ADCSRBADCSRB
-
+
ADC3ADC3
ADC2ADC2
ADC1ADC1
ADC0ADC0
V
CCCC
INPUTINPUT
MUXMUX
CHANNEL
ADIE
ADC IRQADC IRQ
SAMPLE & HOLDSAMPLE & HOLD
COMPARATORCOMPARATOR
INTERNALINTERNAL
REFERENCEREFERENCE
TEMPERATURETEMPERATURE
SENSORSENSOR
AGND
ADC MUX OUTPUTADC MUX OUTPUT
REFS
INTERRUPT FLAGS
ADLAR
ADC7ADC7
ADC6ADC6
ADC5ADC5
ADC4ADC4
ADMUXBADMUXB
MUX5