Datasheet

135
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Table 45. ACIS1/ACIS0 Settings
When changing these bits, the analog comparator interrupt must be disabled. Otherwise, an interrupt can occur when the
bits are changed.
14.1.2 ACSRB – Analog Comparator Control and Status Register B
z Bit 7 – HSEL: Hysteresis Select
When this bit is written logic one, the hysteresis of the analog comparator is enabled. The level of hysteresis is selected
by the HLEV bit.
z Bit 6 – HLEV: Hysteresis Level
When enabled via the HSEL bit, the level of hysteresis can be set using the HLEV bit, as shown in Table 46.
Table 46. Selecting Level of Analog Comparator Hysteresis
z Bit 4 – Res: Reserved Bit
This bit is reserved and will always read as zero.
z Bits 3:2 – ACNMUX[1:0]: Analog Comparator Negative Input Multiplexer
These bits select the source for the negative input of the analog comparator, as shown in Table 47, below.
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle.
0 1 Reserved
1 0 Comparator Interrupt on Falling Output Edge.
1 1 Comparator Interrupt on Rising Output Edge.
Bit 76543210
0x2F (0x4F) HSEL HLEV
– – ACNMUX1 ACNMUX0 ACPMUX1 ACPMUX0 ACSRB
Read/Write R/W R/W R R R/W R/W R/W R/W
Initial Value 0 0000000
HSEL HLEV Hysteresis of Analog Comparator
0 X Not enabled
1
0 20 mV
1 50 mV