Datasheet

134
ATtiny828 [DATASHEET]
8371A–AVR–08/12
14.1 Register Description
14.1.1 ACSRA – Analog Comparator Control and Status Register
z Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to
turn off the analog comparator. This will reduce power consumption in Active and Idle mode.
When changing this bit, the analog comparator Interrupt must be disabled (see ACIE bit). Otherwise, an interrupt can
occur when the bit is changed.
z Bit 6 – ACPMUX2: Analog Comparator Positive Input Multiplexer
Together with ACPMUX1 and ACPMUX0, these bits select the source for the positive input of the analog converter. See
“ACSRB – Analog Comparator Control and Status Register B” on page 135.
z Bit 5 – ACO: Analog Comparator Output
The output of the analog comparator is synchronized and then directly connected to this bit. The synchronization
introduces a delay of 1 - 2 clock cycles.
z Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0.
The analog comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one
to the flag.
z Bit 3 – ACIE: Analog Comparator Interrupt Enable
When this bit is set and the I-bit in the Status Register is set, the analog comparator interrupt is activated. When this bit is
cleared the interrupt is disabled.
z Bit 2 – ACIC: Analog Comparator Input Capture Enable
When this bit is set the input capture function of Timer/Counter1 can be triggered by the analog comparator. The
comparator output is then directly connected to the input capture front-end logic, making the comparator utilize the noise
canceler and edge select features of the Timer/Counter1 input capture interrupt. To make the comparator trigger the
Timer/Counter1 Input Capture interrupt the ICIE1 bit must be set (see “TIMSK1 – Timer/Counter Interrupt Mask Register”
on page 129).
When this bit is cleared, no connection between the analog comparator and the input capture function exists.
z Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the analog comparator interrupt. The different settings are
shown in Table 45.
Bit 76543210
0x30 (0x50) ACD ACPMUX2 ACO ACI ACIE ACIC ACIS1 ACIS0 ACSRA
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 N/A 0 0 0 0 0