Datasheet

132
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Figure 51. Prescaler for Timer/Counter0
Note: 1. The synchronization logic on the input pins (
T0) is shown in Figure 50 on page 131.
13.3 Register Description
13.3.1 GTCCR – General Timer/Counter Control Register
z Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to
the PSR bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted
and can be configured without the risk of advancing during configuration.
When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter starts counting.
z Bit 0 – PSR: Prescaler Reset
When this bit is one, the Timer/Counter prescaler will be Reset. This bit is normally cleared immediately by hardware,
except if the TSM bit is set.
PSR
Clear
clk
T0
Tn
clk
I/O
Synchronization
Bit 7 6 5 4 3 2 1 0
0x23 (0x43) TSM – – – – – – PSR GTCCR
Read/Write R/W R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0