Datasheet

128
ATtiny828 [DATASHEET]
8371A–AVR–08/12
12.11.5 TOCPMCOE – Timer/Counter Output Compare Pin Mux Channel Output Enable
z Bits 7:0 – TOCCnOE: Timer/Counter Output Compare Channel Output Enable
These bits enable the selected output compare channel on the corresponding TOCCn pin, regardless if the output
compare mode is selected, or not.
12.11.6 TCNT1H and TCNT1L – Timer/Counter1
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for
write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and
written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high
byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers”
on page 120.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between
TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units.
12.11.7 OCR1AH and OCR1AL – Output Compare Register 1 A
12.11.8 OCR1BH and OCR1BL – Output Compare Register 1 B
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A
match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1x pin.
Bit 7 6 5 4 3 2 1 0
(0xE2) TOCC7OE TOCC6OE TOCC5OE TOCC4OE TOCC3OE TOCC2OE TOCC1OE TOCC0OE TOCPMCOE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x85) TCNT1[15:8] TCNT1H
(0x84) TCNT1[7:0] TCNT1L
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x89) OCR1A[15:8] OCR1AH
(0x88) OCR1A[7:0] OCR1AL
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x8B) OCR1B[15:8] OCR1BH
(0x8A) OCR1B[7:0] OCR1BL
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0