Datasheet
127
ATtiny828 [DATASHEET]
8371A–AVR–08/12
12.11.3 TCCR1C – Timer/Counter1 Control Register C
z Bit 7 – FOC1A: Force Output Compare for Channel A
z Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode. However, for ensuring
compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode.
When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform
Generation unit. The OC1A/OC1B output is changed according to its COM1x[1:0] bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x[1:0] bits that determine
the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC)
mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
z Bits 5:0 – Res: Reserved Bit
These bits are reserved for future use. To ensure compatibility with future devices, these bits must be set to zero when
the register is written.
12.11.4 TOCPMSA1 and TOCPMSA0 – Timer/Counter Output Compare Pin Mux Selection Registers
z Bits 7:0 – TOCCnS1 and TOCCnS0: Timer/Counter Output Compare Channel Select
TOCCnS1 and TOCCnS bits select which Timer/Counter compare output is routed to the corresponding TOCCn pin. The
two timer/counters provide four possible compare outputs that can be routed to output pins, as shown in the table below.
Table 44. Selecting Timer/Counter Compare Output for TOCCn Pins
Note: 1. See “Alternative Functions of Port C” on page 73.
Bit 7 6 5 4 3 2 1 0
(0x82) FOC1A FOC1B – – – – – – TCCR1C
Read/Write W W R R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0xE9) TOCC7S1 TOCC7S0 TOCC6S1 TOCC6S0 TOCC5S1 TOCC5S0 TOCC4S1 TOCC4S0 TOCPMSA1
(0xE8) TOCC3S1 TOCC3S0 TOCC2S1 TOCC2S0 TOCC1S1 TOCC1S0 TOCC0S1 TOCC0S0 TOCPMSA0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
TOCCnS1 TOCCnS0 TOCCn Output
(1)
0 0 OC0A
0 1 OC0B
1 0 OC1A
1 1 OC1B