Datasheet

126
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is
written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive)
edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register
(ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if
this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM1[3:0] bits located in the TCCR1A and the TCCR1B
Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
z Bit 5 – Res: Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when
register is written.
z Bits 4:3 – WGM1[3:2] : Waveform Generation Mode
See TCCR1A Register description.
z Bits 2:0 – CS1[2:0]: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 46 on page 118 and
Figure 47 on page 119.
Table 43. Clock Select Bit Description
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is
configured as an output. This feature allows software control of the counting.
CS12 CS11 CS10 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clk
I/O
/1 (No prescaling)
0 1 0 clk
I/O
/8 (From prescaler)
0 1 1 clk
I/O
/64 (From prescaler)
1 0 0 clk
I/O
/256 (From prescaler)
1 0 1 clk
I/O
/1024 (From prescaler)
1 1 0 External clock source on T1 pin. Clock on falling edge.
1 1 1 External clock source on T1 pin. Clock on rising edge.