Datasheet

118
ATtiny828 [DATASHEET]
8371A–AVR–08/12
TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values.
12.9 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T1
) is therefore shown as a clock enable signal in the
following figures. The figures include information on when interrupt flags are set, and when the OCR1x Register is
updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 46 shows a timing diagram for
the setting of OCF1x.
Figure 46. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 47 shows the same timing data, but with the prescaler enabled.
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value
New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
Tn
(clk
I/O
/1)
clk
I/O