Datasheet

ATtiny828 [DATASHEET]

8371A–AVR–08/12

12.6.2 Compare Match Blocking by TCNT1 Write

All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even when

the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an

interrupt when the Timer/Counter clock is enabled.

12.6.3 Using the Output Compare Unit

Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks

involved when changing TCNT1 when using any of the Output Compare channels, independent of whether the

Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be

missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable

TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not

write the TCNT1 value equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The

easiest way of setting the OC1x value is to use the Force Output Compare (1x) strobe bits in Normal mode. The OC1x

Be aware that the COM1x[1:0] bits are not double buffered together with the compare value. Changing the COM1x[1:0]

bits will take effect immediately.

12.7 Compare Match Output Unit

The Compare Output Mode (COM1x[1:0]) bits have two functions. The Waveform Generator uses the COM1x[1:0] bits

for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x[1:0] bits control the

OC1x pin output source. Figure 41 shows a simplified schematic of the logic affected by the COM1x[1:0] bit setting.

Figure 41. Compare Match Output Unit, Schematic (non-PWM Mode)

PORT

DDR

OCnx

Waveform

Generator

COMnx1

COMnx0

DATA BUS

FOCnx

clk

I/O