Datasheet

108
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same
technique as for the T1 pin (Figure 50 on page 131). The edge detector is also identical. However, when the noise
canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock
cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in
a Waveform Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
12.5.2 Noise Canceler
The noise canceler uses a simple digital filtering technique to improve noise immunity. Consecutive samples are
monitored in a pipeline four units deep. The signal going to the edge detecter is allowed to change only when all four
samples are equal.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register
B (TCCR1B). When enabled, the noise canceler introduces an additional delay of four system clock cycles to a change
applied to the input and before ICR1 is updated.
The noise canceler uses the system clock directly and is therefore not affected by the prescaler.
12.5.3 Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming
events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register
before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be
incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as
possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is
dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during
operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing
the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge,
the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring
frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used).
12.6 Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals
OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle.
If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x flag is
automatically cleared when the interrupt is executed. Alternatively the OCF1x flag can be cleared by software by writing
a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the Waveform Generation mode (WGM1[3:0]) bits and Compare Output mode (COM1x[1:0]) bits.
The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme
values in some modes of operation (“Modes of Operation” on page 111).
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In
addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform
Generator.
Figure 40 on page 109 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names
indicates the device number (n = 1
for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements
of the block diagram that are not directly a part of the Output Compare unit are gray shaded.
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the
Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The