Datasheet

104
ATtiny828 [DATASHEET]
8371A–AVR–08/12
12. 16-bit Timer/Counter1
12.1 Features
z True 16-bit Design (i.e., Allows 16-bit PWM)
z Two independent Output Compare Units
z Double Buffered Output Compare Registers
z One Input Capture Unit
z Input Capture Noise Canceler
z Clear Timer on Compare Match (Auto Reload)
z Glitch-free, Phase Correct Pulse Width Modulator (PWM)
z Variable PWM Period
z Frequency Generator
z External Event Counter
z Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
12.2 Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and
signal timing measurement.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 37. CPU accessible I/O Registers, including I/O
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in section “Register
Description” on page 123.
Figure 37. 16-bit Timer/Counter Block Diagram
Clock Select
Timer/Counter
DATA B U S
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn