Datasheet

103
ATtiny828 [DATASHEET]
8371A–AVR–08/12
11.9.7 TIFR0 – Timer/Counter Interrupt Flag Register
z Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bit 2 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B. OCF0B is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and
OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
z Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output
Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0
Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
z Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG
I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is
executed.
The setting of this flag is dependent of the WGM0[2:0] bit setting. See Table 36 on page 100.
Bit 76543210
0x15 (0x35) –––––OCF0BOCF0ATOV0TIFR0
Read/Write RRRRRR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0