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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 32 (7x7) 8-Bit 20 MHz I/O number 28
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ATtiny828 [DATASHEET]
8371A–AVR–08/12
counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the
OCR0x Registers.
11.9.4 OCR0A – Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A
match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin.
11.9.5 OCR0B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A
match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin.
11.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register
z Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B
interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the
OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
z Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A
interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when
the OCF0A bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
z Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register – TIFR.
Bit 76543210
0x27 (0x47) OCR0A[7:0] OCR0A
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x28 (0x48) OCR0B[7:0] OCR0B
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0x6E) – – – – – OCIE0B OCIE0A TOIE0 TIMSK0
Read/Write RRRRRR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0