ATtiny828 8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash DATASHEET Features z High Performance, Low Power Atmel® AVR® 8-bit Microcontroller z Advanced RISC Architecture z 123 Powerful Instructions – Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers z Fully Static Operation z Up to 20 MIPS Throughput at 20 MHz z z Non-volatile Program and Data Memories z z z z z 8K Bytes of In-System Programmable Flash Program Memory z Endurance: 10,000 Write/Erase Cycles 256
z Low Power Consumption z Active Mode: 0.2 mA at 1.8V and 1MHz Idle Mode: 30 µA at 1.8V and 1MHz z Power-Down Mode (WDT Enabled): 1 µA at 1.8V z Power-Down Mode (WDT Disabled): 100 nA at 1.8V z Pin Configurations ATtiny828 Pinout in MLF32. 32 31 30 29 28 27 26 25 PC1 (PCINT17/ADC17/TOCC1/INT0/CLKO) PC0 (PCINT16/ADC16/TOCC0/SS/XCK) PD3 (PCINT27/ADC27/SCL/SCK) PD2 (PCINT26/ADC26/RESET/DW) PD1 (PCINT25/ADC25/MISO) PD0 (PCINT24/ADC24/SDA/MOSI) PB7 (PCINT15/ADC15) PB6 (PCINT14/ADC14) Figure 1.
1.1 Pin Description 1.1.1 VCC Supply voltage. 1.1.2 AVCC AVCC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should be externally connected to VCC even if the ADC is not used. If the ADC is used, it is recommended this pin is connected to VCC through a low-pass filter, as described in “Noise Canceling Techniques” on page 145. All pins of Port A and Port B are powered by AVCC. All other I/O pins take their supply voltage from VCC. 1.1.3 GND Ground. 1.1.
standard source capability, while PD2 only has weak drive characteristics due to its use as a reset pin. See Table 103 on page 247 for port drive strength. As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port has alternative pin functions for pin change interrupts, ADC, serial interfaces, and debugWire.
2. Overview ATtiny828 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny828 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 3.
ATtiny828 provides the following features: z 8K bytes of in-system programmable Flash z 512 bytes of SRAM data memory z 256 bytes of EEPROM data memory z 28 general purpose I/O lines z 32 general purpose working registers z An 8-bit timer/counter with two PWM channels z A16-bit timer/counter with two PWM channels z Internal and external interrupts z A 10-bit ADC with 4 internal and 28 external chanels z An ultra-low power, programmable watchdog timer with internal oscillator z A program
3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 4.
Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set. Program Flash memory is divided in two sections; the boot program section and the application program section.
Figure 5. General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 R3 0x03 … ... R12 0x0C R13 0x0D R14 0x0E R15 0x0F R16 0x10 R17 0x11 Special Function … ...
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The stack is mainly used for storing temporary data, local variables and return addresses after interrupts and subroutine calls. The Stack Pointer registers (SPH and SPL) always point to the top of the stack. Note that the stack grows from higher memory locations to lower memory locations.
Figure 8. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 4.8 Register Description 4.8.
4.8.3 SREG – Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 z SREG Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
5. Memories The AVR architecture makes a distinction between program memory and data memory, locating each memory type in a separate address space. Executable code is located in non-volatile program memory (Flash), whereas data can be placed in either volatile (SRAM) or non-volatile memory (EEPROM). See Figure 9, below. Figure 9. Memory Overview.
5.2 Data Memory (SRAM) and Register Files Table 3 shows how the data memory and register files of ATtiny828 are organized. These memory areas are volatile, i.e. they do not retain information when power is removed. Layout of Data Memory and Register Area Table 3.
5.2.3 Extended I/O Register File Following the standard I/O register file, the next 160 locations are reserved for extended I/O registers. ATtiny828 is a complex microcontroller with more peripheral units than can be addressed with the IN and OUT instructions. Registers in the extended I/O area must be accessed using instructions LD/LDD/LDI/LDS and ST/STD/STS. See “Instruction Set Summary” on page 301. See “Register Summary” on page 297 for a list of I/O registers.
5.3 Data Memory (EEPROM) ATtiny828 contains 256 bytes of non-volatile data memory. This EEPROM is organized as a separate data space, in which single bytes can be read and written. All access registers are located in the I/O space. The EEPROM memory layout is summarised in Table 4, below. Table 4. Size of Non-Volatile Data Memory (EEPROM) Device EEPROM Size Address Range ATtiny828 256B 0x00 – 0xFF The internal 8MHz oscillator is used to time EEPROM operations.
5.3.3 Erase In order to prevent unintentional EEPROM writes, a specific procedure must be followed to erase memory locations. To erase an EEPROM memory location follow the procedure below: z Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no other EEPROM operations are in process. If set, wait to clear. z Poll the SPMEN bit in Store Program Memory Control and Status Register (SPMCSR) to make sure no selfprogramming opertaions are in process.
At low supply voltages data in EEPROM can be corrupted in two ways: z The supply voltage is too low to maintain proper operation of an otherwise legitimate EEPROM program sequence. z The supply voltage is too low for the CPU and instructions may be executed incorrectly. EEPROM data corruption is avoided by keeping the device in reset during periods of insufficient power supply voltage. This is easily done by enabling the internal Brown-Out Detector (BOD).
C Code Example void EEPROM_write(unsigned int ucAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
C Code Example unsigned char EEPROM_read(unsigned int ucAddress) { /* Wait for completion of previous write */ while(EECR & (1<
5.4.2 EEDR – EEPROM Data Register Bit 7 6 5 4 3 2 1 0 0x20 (0x40) EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 z EEDR Bits 7:0 – EEDR[7:0]: EEPROM Data For EEPROM write operations, EEDR contains the data to be written to the EEPROM address given in the EEAR Register. For EEPROM read operations, EEDR contains the data read out from the EEPROM address given by EEAR. 5.4.
z Bit 2 – EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set and EEPE written within four clock cycles the EEPROM at the selected address will be programmed. Hardware clears the EEMPE bit to zero after four clock cycles. If EEMPE is zero the EEPE bit will have no effect. z Bit 1 – EEPE: EEPROM Program Enable This is the programming enable signal of the EEPROM.
5.4.6 GPIOR0 – General Purpose I/O Register 0 Bit 7 6 5 4 3 2 1 0 0x1E (0x3E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 GPIOR0 This register may be used freely for storing any kind of data.
6. Clock System Figure 11 presents the principal clock systems and their distribution in ATtiny828. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes and power reduction register bits, as described in “Power Management and Sleep Modes” on page 34. The clock systems is detailed below. Figure 11.
6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.
To ensure stable operation of the MCU it is required to avoid sudden changes in the external clock frequency . A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency. Stable operation for large step changes in system clock frequency is guaranteed when using the system clock prescaler. See “System Clock Prescaler” on page 30. 6.2.
6.3 System Clock Prescaler The ATtiny828 system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 31. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 8 on page 31. 6.3.
5. At least 4ms when reset is disabled. 6.6 Register Description 6.6.1 CLKPR – Clock Prescale Register Bit 7 6 5 4 3 2 1 0 (0x61) – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 z CLKPR See Bit Description Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read zero.
Note: 1. This is the initial value when CKDIV8 fuse has been unprogrammed. 2. This is the initial value when CKDIV8 fuse has been programmed. The device is shipped with the CKDIV8 Fuse programmed. The initial value of clock prescaler bits is determined by the CKDIV8 fuse (see Table 91 on page 227). When CKDIV8 is unprogrammed, the system clock prescaler is set to one and, when programmed, to eight. Any value can be written to the CLKPS bits regardless of the CKDIV8 fuse bit setting.
6.6.3 OSCTCAL0A – Oscillator Temperature Calibration Register A Bit 7 6 5 (0xF0) 4 Read/Write R/W R/W R/W R/W Initial Value z 3 2 1 0 R/W R/W R/W Oscillator Temperature Calibration Data R/W OSCTCAL0A Device Specific Calibration Value Bits 7:0 – Oscillator Temperature Calibration Value The temperature calibration value can be used to trim the calibrated 8MHz oscillator and remove temperature variations from the oscillator frequency. 6.6.
7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
the ACD bit in ACSRA. See “ACSRA – Analog Comparator Control and Status Register” on page 134. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing other clocks to run.
possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 7.3.1 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.
7.4 Register Description 7.4.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – – SM1 SM0 SE Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 z SMCR Bits 7:3 – Res: Reserved Bits These bits are reserved and will always read zero. z Bits 2:1 – SM[1:0]: Sleep Mode Select Bits 1 and 0 These bits select the sleep mode, as shown in Table 10. Table 10.
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. z Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. z Bit 2 – PRSPI: Power Reduction SPI Writing a logic one to this bit shuts down the SPI by stopping the clock to the module.
8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations.
Figure 14. MCU Start-up, RESET Tied to VCC V POT V CC RESET V RST TIME-OUT t TOUT INTERNAL RESET Figure 15. MCU Start-up, RESET Extended Externally V CC V POT > t TOUT RESET TIME-OUT V RST t TOUT INTERNAL RESET 8.2.2 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see section “System and Reset Characteristics” on page 250) will generate a reset, even if the clock is not running.
Figure 16. External Reset During Operation CC 8.2.3 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse. On the falling edge of this pulse, the delay timer starts counting the time-out period tTOUT. See page 41 for details on operation of the Watchdog Timer. Figure 17. Watchdog Reset During Operation CC CK 8.2.4 Brown-out Detection The Brown-Out Detection (BOD) circuit monitors that the VCC level is kept above a configurable trigger level, VBOT.
Figure 18. Brown-out Reset During Operation VCC VBOT+ VBOT- RESET tTOUT TIME-OUT INTERNAL RESET The BOD circuit will not detect a drop in VCC unless the voltage stays below the trigger level for the detection time, tBOD (see “System and Reset Characteristics” on page 250). The BOD circuit has three modes of operation: z Disabled: In this mode of operation VCC is not monitored and, hence, it is recommended only for applications where the power supply remains stable.
Setting BOD Mode of Operation in Sleep Modes Other Than Idle Table 12. BODPD1 BODPD0 Mode of Operation 0 0 Reserved 0 1 Sampled 1 0 Enabled 1 1 Disabled See “Fuse Bits” on page 226. 8.3 Internal Voltage Reference ATtiny828 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The bandgap voltage varies with supply voltage and temperature. 8.3.
Watchdog Timer WDP0 WDP1 WDP2 WDP3 OSC/256K OSC/64K OSC/128K OSC/32K OSC/8K OSC/2K OSC/1K OSC/512 WATCHDOG RESET OSC/16K WATCHDOG PRESCALER 32 kHz ULP OSCILLATOR OSC/4K Figure 19. MUX WDE MCU RESET 8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level.
Assembly Code Example WDT_off: wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, ~(1<
To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 8.5.
If the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. To avoid this situation, the application software should always clear the WDRF flag and the WDE control bit in the initialization routine.
9. Interrupts This section describes the specifics of the interrupt handling. For a general explanation of the AVR interrupt handling, see “Reset and Interrupt Handling” on page 12. 9.1 Interrupt Vectors The interrupt vectors of ATtiny828 are described in Table 16 below. Table 16. Reset and Interrupt Vectors Vector No.
Note: 1. When the IVSEL bit in MCUCR is set, interrupt vectors are moved to the start of the Flash boot section. In this case, the address of each interrupt vector will be the address in this table added to the start address of the Flash boot section. 2. When the BOOTRST fuse is programmed, the device will jump to the boot loader address at reset. See “Entering the Boot Loader Program” on page 216.
Table 17. Reset and Interrupt Vector Placement BOOTRST (1) IVSEL 1 Note: Reset Address Start of Interrupt Vector Table 0 0x000 0x001 1 1 0x000 Boot reset address (2) + 0x001 0 0 Boot reset address (2) 0x001 0 1 Boot reset address (2) Boot reset address (2) + 0x001 1. For the BOOTRST fuse “1” means unprogrammed while “0” means programmed. 2. The boot reset address is shown in Table 82 on page 217.
Assembly Code Example .org 0x0001 rjmp rjmp ... rjmp rjmp ; Set address of next statement INT0_ISR INT1_ISR ; Address 0x0001 ; Address 0x0002 SPM_RDY_ISR RESERVED ; Address 0x0018 ; Address 0x0019 .org 0x0C00 ; Set address of next statement RESET: ; Main program start ; Address 0x0C00 ... Note: See “Code Examples” on page 7.
The pin change interrupts trigger as follows: z Pin Change Interrupt 0 (PCI0): triggers if any enabled PCINT[7:0] pin toggles z Pin Change Interrupt 1 (PCI1): triggers if any enabled PCINT[15:8] pin toggles z Pin Change Interrupt 2 (PCI2): triggers if any enabled PCINT[23:16] pin toggles z Pin Change Interrupt 3(PCI3): triggers if any enabled PCINT[27:24] pin toggles Registers PCMSK0, PCMSK1, PCMSK2, and PCMSK3 control which pins contribute to the pin change interrupts.
Figure 20. Timing of pin change interrupts pin_lat PCINT(0) D pcint_in_(0) Q clk 0 pcint_syn pcint_setflag PCIF pin_sync LE x PCINT(0) in PCMSK(x) clk clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 9.3 Register Description 9.3.
To avoid unintentional changes to this bit, the following sequence must be followed: 9.3.2 1. Write the required signature to the CCP register. See page 14. 2. Within four instruction cycles, write the desired value to IVSEL.
9.3.5 PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x6B) z PCMSK0 Bits 7:0 – PCINT[7:0] : Pin Change Interrupt Mask Bits Each PCINTn bit selects if the pin change interrupt of the corresponding I/O pin is enabled.
9.3.7 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 (0x68) – – – – PCIE3 PCIE2 PCIE1 PCIE0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 z PCICR Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read zero. z Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When this bit and the I-bit of SREG are set the Pin Change Interrupt 3 is enabled. Any change on an enabled PCINT[27:24] pin will cause a PCINT3 interrupt.
z Bit 0 – INT0: External Interrupt Request 0 Enable The external interrupt for pin INT0 is enabled when this bit and the I-bit in the Status Register (SREG) are set. The trigger conditions are set with the ISC0n bits. Activity on the pin will cause an interrupt request even if INT1 has been configured as an output. 9.3.
z Bit 2 – PCIF2: Pin Change Interrupt Flag 2 This bit is set when a logic change on any PCINT[23:16] pin has triggered an interrupt request. Provided that the I-bit in SREG and the PCIE2 bit in PCICR are set, the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
10. I/O Ports 10.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors. The pin driver is strong enough to drive LED displays directly.
Figure 22. General Digital I/O(1) REx Q D PUExn Q CLR RESET Q WEx D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O SLEEP: clk I/O : Note: SLEEP CONTROL I/O CLOCK WEx: REx: WDx: RDx: WRx: RRx: RPx: WPx: WRITE PUEx READ PUEx WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER 1.
The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to be written logic zero. Table 19 summarizes the control signals for the pin value. Table 19. Port Pin Configurations DDxn PORTxn PUExn I/O Pull-up Comment 0 X 0 Input No Tri-state (hi-Z) 0 X 1 Input Yes Sources current if pulled low externally 1 0 0 Output No Output low (sink) 1 0 1 Output Yes NOT RECOMMENDED. Output low (sink) and internal pull-up active.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
10.2.6 Program Example The following code example shows how to set port B pin 0 high, pin 1 low, and define the port pins from 2 to 3 as input with a pull-up assigned to port pin 2. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Figure 25.
The illustration in the figure above serves as a generic description applicable to all port pins in the AVR microcontroller family. Some overriding signals may not be present in all port pins. Table 20 summarizes the function of the overriding signals. The pin and port indexes from Figure 25 on page 64 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternative function. Table 20.
Table 21.
Table 22.
Pin PA3 PA4 PA5 Signal Composition PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT3 • PCIE0) + ADC3D DIEOV PCINT3 • PCIE0 DI PCINT3 Input AIO ADC3 Input PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT4 • PCIE0) + ADC4D DIEOV PCINT4 • PCIE0 DI PCINT4 Input AIO ADC4 Input PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT5 • PCIE0) + ADC5D DIEOV PCINT5 • PCIE0 DI PCINT5 Input AIO ADC5 Input ATtiny828
Pin PA6 PA7 Signal Composition PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT6 • PCIE0) + ADC6D DIEOV PCINT6 • PCIE0 DI PCINT6 Input AIO ADC6 Input PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT7 • PCIE0) + ADC7D DIEOV PCINT7 • PCIE0 DI PCINT7 Input AIO ADC7 Input 10.3.2 Alternative Functions of Port B The alternative functions of port B are shown in Table 23. Table 23.
Pin Function Description of Alternative Function PCINT10 Pin change interrupt source ADC10 Input channel for analog to digital converter (ADC) PCINT11 Pin change interrupt source ADC11 Input channel for analog to digital converter (ADC) PCINT12 Pin change interrupt source ADC12 Input channel for analog to digital converter (ADC) PCINT13 Pin change interrupt source ADC13 Input channel for analog to digital converter (ADC) PCINT14 Pin change interrupt source ADC14 Input channel for analo
Pin PB1 PB2 Signal Composition PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT9 • PCIE1) + ADC9D DIEOV PCINT9 • PCIE1 DI PCINT9 Input AIO ADC9 Input PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT10 • PCIE1) + ADC10D DIEOV PCINT10 • PCIE1 DI PCINT10 Input AIO ADC10 Input ATtiny828 [DATASHEET] 8371A–AVR–08/12 71
Pin PB3 PB4 PB5 Signal Composition PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT11 • PCIE1) + ADC11D DIEOV PCINT11 • PCIE1 DI PCINT11 Input AIO ADC11 Input PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT12 • PCIE1) + ADC12D DIEOV PCINT12 • PCIE1 DI PCINT12 Input AIO ADC12 Input PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT13 • PCIE1) + ADC13D DIEOV PCINT13 • PCIE1 DI PCINT13 Input AIO ADC13 I
Pin PB6 PB7 Signal Composition PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT14 • PCIE1) + ADC14D DIEOV PCINT14 • PCIE1 DI PCINT14 Input AIO ADC14 Input PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE (PCINT15 • PCIE1) + ADC15D DIEOV PCINT15 • PCIE1 DI PCINT15 Input AIO ADC15 Input 10.3.3 Alternative Functions of Port C The alternative functions of port C are shown in Table 25. Table 25.
Pin PC1 PC2 Function Description of Alternative Function PCINT17 Pin change interrupt source ADC17 Input channel for analog to digital converter (ADC) TOCC1 Timer/counter output compare, channel 1 (1) INT0 External interrupt request 0 CLKO System clock output (3) PCINT18 Pin change interrupt source ADC18 Input channel for analog to digital converter (ADC) TOCC2 Timer/counter output compare, channel 2 (1) RXD USART serial data input INT1 External interrupt request 1 PCINT19 Pin chan
2. When SPI is enabled as a slave, this pin is automatically configured as an input, regardless of the data direction bit of the pin. When SPI is enabled as a master normal pin control of data direction is resumed. 3. When the CKOUT fuse is programmed, the system clock is output on this pin, regardless of pin settings. The clock is also output when the device is reset. Table 26, below, summarises the override signals used by the alternative functions of the port.
Pin PC2 Signal Composition PUOE 0 PUOV 0 DDOE RXEN DDOV 0 PVOE TOCC2OE PVOV TOCC2_OUT PTOE 0 DIEOE (PCINT18 • PCIE2) + ADC18D + (RXEN z SFDE) + INT1 DIEOV PCINT18 • PCIE2 + (RXEN z SFDE) + INT1 DI PCINT18 Input / INT1 Input / RXD_IN AIO ADC18 Input ATtiny828 [DATASHEET] 8371A–AVR–08/12 76
Pin PC3 PC4 PC5 Signal Composition PUOE TXEN PUOV 0 DDOE TXEN DDOV 0 PVOE TOCC3OE + TXEN PVOV TXEN z TXD_OUT + TXEN z TOCC3_OUT PTOE 0 DIEOE (PCINT19 • PCIE2) + ADC19D DIEOV PCINT19 • PCIE2 DI PCINT19 Input AIO ADC19 Input PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE TOCC4OE PVOV TOCC4_OUT PTOE 0 DIEOE (PCINT20 • PCIE2) + ADC20D DIEOV PCINT20 • PCIE2 DI PCINT20 Input AIO ADC20 Input PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE TOCC5OE PVOV TOCC5_OUT PTOE 0 DIEOE (PCI
Pin PC6 PC7 Notes: 1.
Table 27.
Table 28.
Pin PD3 Note: 10.4 1. Signal Composition PUOE 0 PUOV 0 DDOE TWEN + (SPE z MSTR) DDOV TWEN z SCL_OUT PVOE TWEN + (SPE z MSTR) PVOV TWEN z SPE z MSTR z SCK_OUT PTOE 0 DIEOE (PCINT27 • PCIE3) + ADC27D DIEOV PCINT27 • PCIE3 DI PCINT27 Input / SCK_IN AIO ADC27 Input / SCL_IN RSTDISBL is 1 when the fuse bit is “0” (programmed) Register Description 10.4.
10.4.2 PUED – Port D Pull-Up Enable Control Register Bit 7 6 5 4 3 2 1 0 0x0F (0x2F) – – – – PUED3 PUED2 PUED1 PUED0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 z PUED Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read zero. z Bits 3:0 – PUED[3:0]: Pull-Up Enable Bits When a pull-up enable bit, PUEDn, is set the pull-up resistor on the equivalent port pin, PDn, is enabled. 10.4.
10.4.5 PIND – Port D Input Pins Bit 7 6 5 4 3 2 1 0 0x0C (0x2C) – – – – PIND3 PIND2 PIND1 PIND0 Read/Write R R R R R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A z PIND Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read zero. z Bits 3:0 – PIND[3:0]: Port Input Data Regardless of the setting of the data direction bit, the value of the port pin PDn can be read through the PINDn bit.
10.4.9 PINC – Port C Input Pins Bit 7 6 5 4 3 2 1 0 0x08 (0x28) PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A z PINC Bits 7:0 – PINC[7:0]: Port Input Data Regardless of the setting of the data direction bit, the value of the port pin PCn can be read through the PINCn bit. Writing a logic one to PINCn toggles the value of PORTCn, regardless of the value in DDCn. 10.4.
10.4.13 PINB – Port B Input Pins Bit 7 6 5 4 3 2 1 0 0x04 (0x24) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A z PINB Bits 7:0 – PINB[7:0]: Port Input Data Regardless of the setting of the data direction bit, the value of the port pin PBn can be read through the PINBn bit. Writing a logic one to PINBn toggles the value of PORTBn, regardless of the value in DDBn. 10.4.
10.4.17 PINA – Port A Input Pins Bit 7 6 5 4 3 2 1 0 0x00 (0x20) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A z PINA Bits 7:0 – PINA[7:0]: Port Input Data Regardless of the setting of the data direction bit, the value of the port pin PAn can be read through the PINAn bit. Writing a logic one to PINAn toggles the value of PORTAn, regardless of the value in DDAn.
11. 8-bit Timer/Counter0 with PWM 11.1 Features z Two Independent Output Compare Units z Double Buffered Output Compare Registers z Clear Timer on Compare Match (Auto Reload) z Glitch Free, Phase Correct Pulse Width Modulator (PWM) z Variable PWM Period z Frequency Generator z Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
For actual placement of I/O pins, refer to Figure 1 on page 2 (MLF), and Figure 2 on page 2 (TQFP). Also, see “TOCPMSA1 and TOCPMSA0 – Timer/Counter Output Compare Pin Mux Selection Registers” on page 127, and “TOCPMCOE – Timer/Counter Output Compare Pin Mux Channel Output Enable” on page 128. 11.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.
Figure 27. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count direction clear clkTn top bottom Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clkT0 in the following. Signalize that TCNT0 has reached maximum value.
Figure 28. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn 8-BIT COMPARATOR OCFnx (Int.Req.) top bottom WAVEFORM GENERATOR OCnx FOCn WGMn[2:0] COMnX[1:0] The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
Be aware that the COM0x[1:0] bits are not double buffered together with the compare value. Changing the COM0x[1:0] bits will take effect immediately. 11.6 Compare Match Output Unit The Compare Output mode (COM0x[1:0]) bits have two functions. The Waveform Generator uses the COM0x[1:0] bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x[1:0] bits control the OC0x pin output source.
A change of the COM0x[1:0] bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the Force Output Compare bits. See “TCCR0B – Timer/Counter Control Register B” on page 100. 11.7 Modes of Operation The mode of operation, i.e.
CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A[1:0] = 1).
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Figure 32. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx[1:0] = 2) OCxn (COMnx[1:0] = 3) Period 1 2 3 In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 32.
At the very start of period 2 in Figure 32 on page 95 OCnx has a transition from high to low even though there is no Compare Match. The point of this transition is to guaratee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. 11.8 z OCR0x changes its value from TOP, like in Figure 32 on page 95. When the OCR0x value is TOP the OCnx pin value is the same as the result of a down-counting Compare Match.
Figure 35. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 36 on page 97 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 36.
When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the WGM0[2:0] bit setting. Table 30 shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or CTC mode (non-PWM). Table 30. Compare Output Mode, non-PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected.
z Bits 5:4 – COM0B[1:0] : Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of COM0B[1:0] bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. The Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of COM0B[1:0] bits depend on WGM0[2:0] bit setting.
z Bits 3:2 – Res: Reserved Bits These bits are reserved and will always read zero. z Bits 1:0 – WGM0[1:0] : Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 36.
z Bit 6 – FOC0B: Force Output Compare B The FOC0B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B[1:0] bits setting. Note that the FOC0B bit is implemented as a strobe.
counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers. 11.9.4 OCR0A – Output Compare Register A Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x27 (0x47) OCR0A[7:0] OCR0A The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0).
11.9.7 TIFR0 – Timer/Counter Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x15 (0x35) – – – – – OCF0B OCF0A TOV0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 z TIFR0 Bits 7:3 – Res: Reserved Bits These bits are reserved and will always read zero. z Bit 2 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B.
12. 16-bit Timer/Counter1 12.1 Features z True 16-bit Design (i.e.
For actual placement of I/O pins, refer to Figure 1 on page 2 (MLF), and Figure 2 on page 2 (TQFP). Also, see “TOCPMSA1 and TOCPMSA0 – Timer/Counter Output Compare Pin Mux Selection Registers” on page 127, and “TOCPMCOE – Timer/Counter Output Compare Pin Mux Channel Output Enable” on page 128. Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel.
12.4 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 38 shows a block diagram of the counter and its surroundings. Figure 38. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. Figure 39.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 50 on page 131). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles.
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitchfree. Figure 40. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.
12.6.2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. 12.6.
The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1x[1:0] bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset occur, the OC1x Register is reset to “0”. The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x[1:0] bits are set.
also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 42 on page 112. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 42.
rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A.
Figure 44. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx[1:0] = 2) OCnx (COMnx[1:0] = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM.
The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 12.8.
Figure 45. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx[1:0] = 2) OCnx (COMnx[1:0] = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM).
TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 12.9 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering).
Figure 47. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 48 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
Figure 49. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx 12.10 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access.
Assembly Code Example ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Example unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: See “Code Examples” on page 7. The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
C Code Example unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: See “Code Examples” on page 7. The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how to do an atomic write of the TCNT1 Register contents.
C Code Example void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; } Note: See “Code Examples” on page 7. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 12.10.
Compare Output Mode, non-PWM Table 39. COM1A1 COM1B1 COM1A0 COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected 0 1 Toggle OC1A/OC1B on Compare Match 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level) 1 1 Set OC1A/OC1B on Compare Match (Set output to high level). Description Table 40 shows COM1x[1:0] bit functionality when WGM1[3:0] bits are set to fast PWM mode. Compare Output Mode, Fast PWM Table 40.
z Bits 1:0 – WGM1[1:0]: Waveform Generation Mode Combined with the WGM1[3:2] bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 42. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (“Modes of Operation” on page 111). Table 42.
z Bit 6 – ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1).
12.11.3 TCCR1C – Timer/Counter1 Control Register C Bit 7 6 5 4 3 2 1 0 FOC1A FOC1B – – – – – – Read/Write W W R R R R R R Initial Value 0 0 0 0 0 0 0 0 (0x82) z Bit 7 – FOC1A: Force Output Compare for Channel A z Bit 6 – FOC1B: Force Output Compare for Channel B TCCR1C The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode.
12.11.5 TOCPMCOE – Timer/Counter Output Compare Pin Mux Channel Output Enable Bit 7 6 5 4 3 2 1 0 TOCC7OE TOCC6OE TOCC5OE TOCC4OE TOCC3OE TOCC2OE TOCC1OE TOCC0OE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xE2) z TOCPMCOE Bits 7:0 – TOCCnOE: Timer/Counter Output Compare Channel Output Enable These bits enable the selected output compare channel on the corresponding TOCCn pin, regardless if the output compare mode is selected, or not.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 120. 12.11.
12.11.11TIFR1 – Timer/Counter Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 z TIFR1 Bits 7, 6, 4, 3 – Res: Reserved Bit These bits are reserved for future use. To ensure compatibility with future devices, these bits must be set to zero when the register is written.
13. Timer/Counter Prescaler Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counters. Tn is used as a general name, n = 0, 1. The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
Figure 51. Prescaler for Timer/Counter0 clk I/O Clear PSR Tn Synchronization clkT0 Note: 13.3 1. The synchronization logic on the input pins (T0) is shown in Figure 50 on page 131. Register Description 13.3.
14. Analog Comparator The analog comparator compares the input values on the positive pin (AIN0) and negative pin (AIN1). When the voltage on AIN0 is higher than the voltage on AIN1, the Analog Comparator Output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the analog comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 52. Figure 52.
14.1 Register Description 14.1.1 ACSRA – Analog Comparator Control and Status Register Bit 7 6 5 4 3 2 1 0 0x30 (0x50) ACD ACPMUX2 ACO ACI ACIE ACIC ACIS1 ACIS0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 z ACSRA Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator.
ACIS1/ACIS0 Settings Table 45. ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. When changing these bits, the analog comparator interrupt must be disabled. Otherwise, an interrupt can occur when the bits are changed. 14.1.
Source Selection for Analog Comparator Negative Input Table 47. ACNMUX1 ACNMUX0 Analog Comparator Negative Input 0 0 AIN1 pin 0 1 Output of ADC multiplexer 1 0 1 1 Reserved z Bits 1:0 – ACPMUX[1:0]: Analog Comparator Positive Input Multiplexer Together with ACPMUX2, these bits select the source for the positive input of the analog comparator, as shown in Table 48, below. Table 48.
15. Analog to Digital Converter 15.1 Features z 10-bit Resolution z 1 LSB Integral Non-linearity z ± 2 LSB Absolute Accuracy z 15µs Conversion Time z 15 kSPS at Maximum Resolution z 28 Multiplexed Single Ended Input Channels z Temperature Sensor Input Channel z Optional Left Adjustment for ADC Result Readout z 0 - VCC ADC Input Voltage Range z 1.
Figure 53. Analog to Digital Converter Block Schematic ADCH+ADCL ADIE ADEN ADPS0 ADPS1 ADPS2 ADATE ADCSRA ADSC ADTS[2:0] ADCSRB ADC IRQ TRIGGER SELECT PRESCALER ADIF CHANNEL START DECODER ADC9:0 ADLAR MUX[4:0] ADMUXA MUX5 REFS ADMUXB INTERRUPT FLAGS 8-BIT DATA BUS CONVERSION LOGIC VCC 10-BIT DAC INTERNAL REFERENCE + SAMPLE & HOLD COMPARATOR TEMPERATURE SENSOR ADC7 ADC6 ADC MUX OUTPUT ADC5 INPUT MUX ADC4 ADC3 ADC2 ADC1 ADC0 AGND 15.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC converts an analog input voltage to a 10-bit digital value using successive approximation. The minimum value represents GND and the maximum value represents the reference voltage.
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
Figure 56. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample & Hold MUX and REFS Update The actual sample-and-hold takes place 4 ADC clock cycles after the start of a normal conversion and 15 ADC clock cycles after the start of a first conversion.
Figure 58. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 Next Conversion 13 9 14 15 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. See Figure 59. Figure 59.
Table 49. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 15 26 Normal conversions 4 15 4.5 15.5 4 15 Condition Auto Triggered conversions Free Running conversion 15.6 Changing Channel or Reference Selection The MUX and REFS bits are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion.
15.7 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode. This reduces noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: z Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled.
15.9 Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. When conversion accuracy is critical, the noise level can be reduced by applying the following techniques: z Keep analog signal paths as short as possible. z Make sure analog tracks run over the analog ground plane. z Keep analog tracks well away from high-speed switching digital tracks.
z Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 62. Offset Error Output Code Ideal ADC Actual ADC Offset Error z VREF Input Voltage Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 63.
z Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 64. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF z Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 65.
z Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. z Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB. 15.
15.13 Register Description 15.13.1 ADMUXA – ADC Multiplexer Selection Register A Bit 7 6 5 4 3 2 1 0 (0x7C) – – – MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 z ADMUXA Bits 4:0 – MUX[4:0] : Analog Channel and Gain Selection Bits These bits together with MUX5 in ADMUXB select which analog input is connected to the ADC. See Table 51. Table 51.
MUX[5:0] Single Ended Input Pin 011000 ADC24 PD0 011001 ADC25 PD1 011010 ADC26 PD2 011011 ADC27 PD3 011100 Ground GND 011101 Internal 1.1V reference (1) (internal) 011110 Temperature sensor (2) (internal) 011111 Supply voltage VCC Reserved (not connected) 100000 – 111111 Notes: 1. 2. After switching to internal voltage reference the ADC requires a settling time of 1ms before measurements are stable. Conversions starting before this may not be reliable.
z Bit 0 – MUX5: Analog Channel and Gain Selection Bit This bit together with MUX[4:0] in ADMUXA select which analog input is connected to the ADC. See Table 51 on page 149. 15.13.3 ADCL and ADCH – ADC Data Register 15.13.3.
z Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 26 ADC clock cycles instead of the normal 15. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress.
15.13.5 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – – – – ADLAR ADTS2 ADTS1 ADTS0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 z ADCSRB Bit 5 – Res: Reserved Bit Thisis a reserved bit. For compatibility with future devices always write this bit to zero. z Bit 3 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
15.13.6 DIDR0 – Digital Input Disable Register 0 Bit 7 6 5 4 3 2 1 0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7E) z DIDR0 Bits 7:0 – ADC7D:ADC0D : ADC[7:0] Digital Input Disable When an analog signal is applied to ADCn and the digital input of the pin is not needed, the ADCnD bit should be set to reduce power consumption.
16. SPI – Serial Peripheral Interface 16.1 Features z Full-duplex, Three-wire Synchronous Data Transfer z Master or Slave Operation z LSB First or MSB First Data Transfer z Seven Programmable Bit Rates z End of Transmission Interrupt Flag z Write Collision Flag Protection z Wake-up from Idle Mode z Double Speed (CK/2) Master SPI Mode Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between ATtiny828 and peripheral devices, or between several AVR devices.
To enable the SPI module, the PRSPI bit in the Power Reduction Register must be written to zero. See “PRR – Power Reduction Register” on page 37. The interconnection between Master and Slave CPUs with SPI is shown in Figure 67 on page 156. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
Table 55. Pin SPI Pin Overrides Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: See “Alternative Port Functions” on page 63 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
C Code Example void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<
C Code Example void SPI_SlaveInit(void) { /* Set MISO output, all others input */ DDR_SPI = (1<
16.4 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 68 on page 160 and Figure 69 on page 160. Figure 68. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Figure 69.
Table 56. SPI Modes SPI Mode 16.5 Conditions Leading Edge Trailing eDge 0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) Register Description 16.5.
z Bit 2 – CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 68 and Figure 69 for an example. The CPOL functionality is summarized below: CPHA Functionality Table 58. z CPHA Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample Bits 1:0 – SPR[1:0]: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master.
z Bits 5:1 – Res: Reserved Bits These bits are reserved and will always read as zero. z Bit 0 – SPI2X: Double SPI Speed Bit When this bit is set the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 59 on page 162). This means that the minimum SCK period will be two I/O clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fclk_I/O/4 or lower. 16.5.
17. USART 17.
For USART pin placement, see Figure 1 on page 2 and “Alternative Port Functions” on page 63. The dashed boxes in the block diagram of Figure 70 illustrate the three main parts of the USART, as follows(listed from the top): z Clock generator z Transmitter z Receiver The clock generation logic consists of synchronization logic (for external clock input in synchronous slave operation), and the baud rate generator. The transfer clock pin (XCK) is only used in synchronous transfer mode.
z Normal asynchronous mode z Double speed asynchronous mode z Master synchronous mode z Slave synchronous mode The UMSEL bit (see “UCSRC – USART Control and Status Register C” on page 186) selects between asynchronous and synchronous operation. In asynchronous mode, the speed is controlled by the U2X bit (see “UCSRA – USART Control and Status Register A” on page 184).
17.3.2 Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2X bit ( see “UCSRA – USART MSPIM Control and Status Register A” on page 196). Setting this bit only has effect in asynchronous mode of operation. In synchronous mode of operation this bit should be cleared. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication.
17.4 Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: z Start bit: 1 z Data bits: 5, 6, 7, 8, or 9 z Parity bit: no, even, or odd parity z Stop bits: 1, or 2 A frame begins with the start bit followed by the least significant data bit.
PEVEN PODD dn Parity bit using even parity Parity bit using odd parity Data bit n of the character If used, the parity bit is located between the last data bit and the first stop bit of a serial frame. 17.5 USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and, depending on the method of use, enabling the transmitter or the receiver.
C Code Example(1) void USART_Init( unsigned int baud ) { /* Set baud rate */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<
C Code Example(1) void USART_Transmit( unsigned char data ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<
C Code Example(1)(2) void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<
17.6.5 Disabling the Transmitter Clearing TXEN will disable the transmitter but the change will not become effective before any ongoing and pending transmissions are completed, i.e. not before the transmit shift register and transmit buffer register are cleared of data to be transmitted. When disabled, the transmitter will no longer override the TxD pin. 17.
17.7.2 Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ = 7) the ninth bit must be read from the RXB8 bit before reading the low bits from UDR. This rule applies to the FE, DOR and UPE status flags, as well. Status bits must be read before data from UDR, since reading UDR will change the state of the receive buffer FIFO and, consequently, state of TXB8, FE, DOR and UPE bits.
C Code Example(1) unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* Wait for data to be received */ while ( !(UCSRA & (1<> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. See “Code Examples” on page 7.
protocol handling. The flag is not affected by the USBS bit, since the receiver ignores all stop bits, except the first. For compatibility with future devices, this bit must always be cleared when writing UCSRA. z The Data OverRun flag (DOR) indicates data loss due to a receiver buffer full condition. A data overrun situation occurs when the receive buffer is full (two characters), there is a new character waiting in the receive shift register, and a new start bit is detected.
17.8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the receiver.
boxes. The majority voting process is done as follows: If two or all three samples have high levels, the received bit is registered to be a logic one. If two, or all three samples have low levels, the received bit is registered to be a logic zero. This majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the receiver only uses the first stop bit of a frame.
Table 61. Recommended Maximum Receiver Baud Rate Error in Normal Speed Mode D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67 / -6.8 ± 3.0 6 94.12 105.79 +5.79 / -5.88 ± 2.5 7 94.81 105.11 +5.11 / -5.19 ± 2.0 8 95.36 104.58 +4.58 / -4.54 ± 2.0 9 95.81 104.14 +4.14 / -4.19 ± 1.5 10 96.17 103.78 +3.78 / -3.83 ± 1.5 Table 62.
When using the feature without start interrupt, the start detection logic activates the internal 8 MHz oscillator and the USART clock while the frame is being received, only. Other clocks remain stopped until the Receive Complete Interrupt wakes up the MCU. For more details, see “UCSRD – USART Control and Status Register D” on page 188. 17.
especially for large serial frames (see “Asynchronous Operational Range” on page 178). The error values are calculated using the following equation: BaudRate Closest Match Error[%] = ⎛ -------------------------------------------------- – 1⎞ • 100% ⎝ ⎠ BaudRate Table 63. Examples of UBRR Settings for Commonly Used Oscillator Frequencies fosc = 1.0000MHz fosc = 1.8432MHz fosc = 2.0000MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 25 0.2% 51 0.
fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.
fosc = 8.0000MHz fosc = 11.0592MHz fosc = 14.7456MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8% – – 0 0.0% – – – – 0 -7.8% 1 -7.8% 1M Max. (1) 1. U2Xn = 0 U2Xn = 1 0.5 Mbps 1 Mbps U2Xn = 0 691.2 kbps U2Xn = 1 1.3824 Mbps U2Xn = 0 921.6 kbps U2Xn = 1 1.8432 Mbps UBRR = 0, Error = 0.0% Table 66.
17.11 Register Description 17.11.1 UDR – USART I/O Data Register Bit 7 6 5 4 3 2 1 0 (0xC6) RXB[7:0] UDR (Read) (0xC6) TXB[7:0] UDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART transmit data buffer and USART receive data buffer registers share the same I/O address, referred to as USART Data Register, or UDR. Data written to UDR goes to the Transmit Data Buffer register (TXB).
z Bit 4 – FE: Frame Error This bit is set if the next character in the receive buffer had a frame error when received (i.e. when the first stop bit of the next character in the receive buffer is zero). This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing the register. z Bit 3 – DOR: Data OverRun This bit is set if a Data OverRun condition is detected.
z Bit 4 – RXEN: Receiver Enable Writing this bit to one enables the USART Receiver. When enabled, the receiver will override normal port operation for the RxD pin. Disabling the receiver will flush the receive buffer, invalidating FE, DOR, and UPE Flags. z Bit 3 – TXEN: Transmitter Enable Writing this bit to one enables the USART Transmitter. When enabled, the transmitter will override normal port operation for the TxD pin.
z Bits 5:4 – UPM1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM setting. If a mismatch is detected, the UPE flag is set. Parity Mode Selection Table 68.
z Bit 0 – UCPOL: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Clock Polarity Settings Table 71. Transmitted Data Changed (Output of TxD Pin) Received Data Sampled (Input on RxD Pin) 0 Rising XCK Edge Falling XCK Edge 1 Falling XCK Edge Rising XCK Edge UCPOL 17.11.
For more information, see “Start Frame Detection” on page 179. z Bits 4:0 – Res: Reserved Bits These bits are reserved and will always read zero. 17.11.
18. USART in SPI Mode 18.1 Features z Full Duplex, Three-wire Synchronous Data Transfer z Master Operation z Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3) z LSB First or MSB First Data Transfer (Configurable Data Order) z Queued Operation (Double Buffered) z High Resolution Baud Rate Generator z High Speed Operation (fXCKmax = fCK/2) z Flexible Interrupt Generation 18.
18.4 SPI Data Modes and Timing There are four combinations of XCK (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHA and UCPOL. The data transfer timing diagrams are shown in Figure 77. Data bits are shifted out and latched in on opposite edges of the XCK signal, ensuring sufficient time for data signals to stabilize. The UCPOL and UCPHA functionality is summarized in Table 74.
16-bit data transfer can be achieved by writing two data bytes to UDR. A USART Transmit Complete interrupt will then signal that the 16-bit value has been shifted out. 18.5.1 USART MSPIM Initialization The USART in MSPIM mode has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting master mode of operation, setting frame format and enabling the transmitter and the receiver. Only the transmitter can operate independently.
C Code Example(1) void USART_Init( unsigned int baud ) { UBRR = 0; /* Setting the XCK port pin as output, enables master mode. */ XCK_DDR |= (1<
Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRA, UDRE rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDR,r16 USART_MSPIM_Wait_RXC: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_MSPIM_Wait_RXC ; Get and return received data from buffer in r16, UDR ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<
18.7 AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: z Master mode timing diagram z The UCPOL bit functionality is identical to the SPI CPOL bit z The UCPHA bit functionality is identical to the SPI CPHA bit z The UDORD bit functionality is identical to the SPI DORD bit However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI.
18.8.2 UCSRA – USART MSPIM Control and Status Register A Bit 7 6 5 4 3 2 1 0 (0xC0) RXC TXC UDRE – – – – – Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 1 1 0 z UCSRA Bit 7 – RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data).
z Bit 4 – RXEN: Receiver Enable Writing this bit to one enables the USART Receiver in MSPIM mode. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXEN=1 and TXEN=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported.
z Bit 1 – UCPHA: Clock Phase The UCPHA bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCK. See “SPI Data Modes and Timing” on page 191 for details. z Bit 0 – UCPOL: Clock Polarity The UCPOL bit sets the polarity of the XCK clock. The combination of the UCPOL and UCPHA bit settings determine the timing of the data transfer. See “SPI Data Modes and Timing” on page 191 for details. 18.8.
19. I2C Compatible, Two-Wire Slave Interface 19.
Figure 78. TWI Bus Topology A unique address is assigned to all slave devices connected to the bus, and the master will use this to address a slave and initiate a data transaction. 7-bit or 10-bit addressing can be used. Several masters can be connected to the same bus, and this is called a multi-master environment. An arbitration mechanism is provided for resolving bus ownership between masters since only one master device may own the bus at any given time.
The master provides the clock signal for the transaction, but a device connected to the bus is allowed to stretch the low level period of the clock to decrease the clock speed. 19.3.1 Electrical Characteristics The TWI follows the electrical specifications and timing of I2C and SMBus. See “Two-Wire Serial Interface Characteristics” on page 252 and “Compatibility with SMBus” on page 205. 19.3.
19.3.4 Address Packet After the START condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is always transmitted by the Master. A slave recognizing its address will ACK the address by pulling the data line low the next SCL cycle, while all other slaves should keep the TWI lines released, and wait for the next START and address. The 7-bit address, the R/W bit and the acknowledge bit combined is the address packet.
Given that the slave acknowledges the address, the master can start receiving data from the slave. There are no limitations to the number of data packets that can be transferred. The slave transmits the data while the master signals ACK or NACK after each data byte. The master terminates the transfer with a NACK before issuing a STOP condition. Figure 84 illustrates a combined transaction. A combined transaction consists of several read and write transactions separated by a Repeated START conditions (Sr).
Figure 86. TWI Arbitration Figure 86 shows an example where two TWI masters are contending for bus ownership. Both devices are able to issue a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while DEVICE2 is transmitting a low level. Arbitration between a repeated START condition and a data bit, a STOP condition and a data bit, or a repeated START condition and STOP condition are not allowed and will require special handling by software. 19.3.
case) has completed its low period it releases the SCL line. However, the SCL line will not go high before all masters have released it. Consequently the SCL line will be held low by the device with the longest low period (DEVICE2). Devices with shorter low periods must insert a wait-state until the clock is released. All masters start their high period when the SCL line is released by all devices and has become high.
19.4.1 Receiving Address Packets When the TWI slave is properly configured, it will wait for a START condition to be detected. When this happens, the successive address byte will be received and checked by the address match logic, and the slave will ACK the correct address. If the received address is not a match, the slave will not acknowledge the address and wait for a new START condition. The slave Address/Stop Interrupt Flag is set when a START condition succeeded by a valid address packet is detected.
19.5 Register Description 19.5.1 TWSCRA – TWI Slave Control Register A Bit 7 6 5 4 3 2 1 0 TWSHE – TWDIE TWASIE TWEN TWSIE TWPME TWSME Read/Write R/W R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB8) z TWSCRA Bit 7 – TWSHE: TWI SDA Hold Time Enable When this bit is set the internal hold time on SDA with respect to the negative edge on SCL is enabled. z Bit 6 – Res: Reserved Bit This bit is reserved and will always read as zero.
19.5.2 TWSCRB – TWI Slave Control Register B Bit 7 6 5 4 3 2 1 0 (0xB9) – – – – – TWAA TWCMD1 TWCMD0 Read/Write R R R R R R/W W W Initial Value 0 0 0 0 0 0 0 0 z TWSCRB Bits 7:3 – Res: Reserved Bits These bits are reserved and will always read as zero. z Bit 2 – TWAA: TWI Acknowledge Action This bit defines the slave's acknowledge behavior after an address or data byte has been received from the master.
TWCMD[1:0] TWDIR Operation Used in response to an Address Byte (TWASIF is set) 0 Execute Acknowledge Action, then receive next byte 1 Execute Acknowledge Action, then set TWDIF 11 Used in response to a Data Byte (TWDIF is set) 0 Execute Acknowledge Action, then wait for next byte 1 No action Writing the TWCMD bits will automatically release the SCL line and clear the TWCH and slave interrupt flags. TWAA and TWCMDn bits can be written at the same time.
This bit is read-only. When zero, the most recent acknowledge bit from the maser was ACK and, when one, the most recent acknowledge bit was NACK. z Bit 3 – TWC: TWI Collision This bit is set when the slave was not able to transfer a high data bit or a NACK bit. When a collision is detected, the slave will commence its normal operation, and disable data and acknowledge output. No low values are shifted out onto the SDA line. This bit is cleared by writing a one to it.
19.5.5 TWSD – TWI Slave Data Register Bit 7 6 5 4 (0xBD) 3 2 1 0 TWSD[7:0] TWSD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware.
20. debugWIRE On-chip Debug System 20.
When designing a system where debugWIRE will be used, the following must be observed: 20.4 z Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. z Connecting the RESET pin directly to VCC will not work. z Capacitors inserted on the RESET pin must be disconnected when using debugWire. z All external reset sources must be disconnected.
21. Self-Programming with Boot Loader and Read-While-Write 21.
In addition to the application and boot loader areas, the Flash is also divided into two fixed sections; the Read-WhileWrite (RWW) and the No Read-While-Write (NRWW) section.
21.4.1 RWW – Read-While-Write Section When the boot loader is programming a page inside the RWW section, it is possible to read code from the Flash, but only code that is located in the NRWW section. During programming, the software must ensure that the RWW section is not read. If the software during programming tries to read code located inside the RWW section (i.e., by a call/jmp/lpm or an interrupt), it may end up in an unknown state.
Table 82. Setting the Size of Application and Boot Loader Sections Application Section BOOTSZ1 BOOTSZ0 0 0 0 1 Start Boot Loader Section End Start (1) 0xBFF 0xC00 0xDFF 0xE00 0x000 Note: End Size (words) 1024 512 0xFFF 1 0 0xEFF 0xF00 256 1 1 0xF7F 0xF80 128 1. Start of boot loader section = boot reset address. Boot Loader Section options are illustrated in Figure 91, below. Figure 91. Addr. Flash Memory Sections vs. BOOTSZ Fuse Bits.
21.7 Boot Loader Lock Bits The boot loader has two separate sets of lock bits, which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can choose any of the following: z Protect the entire Flash from a software update by the MCU z Protect only the Boot Loader Flash section from a software update by the MCU z Protect only the Application Flash section from a software update by the MCU z Allow software update in the entire Flash.
1. 2. Either, fill the buffer before a Page Erase: 1. Fill temporary page buffer 2. Perform a Page Erase 3. Perform a Page Write Or, fill the buffer after Page Erase: 1. Perform a Page Erase 2. Fill temporary page buffer 3. Perform a Page Write When using alternative 1, the boot loader provides an effective read-modify-write feature, which allows the user software to first read the page, do the necessary changes, and then write back the modified data.
Figure 92. Addressing the Flash During SPM BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PCWORD WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: INSTRUCTION WORD 00 01 02 PAGEEND Variables used in Figure 92 are explained in Table 83, below. Table 83. Variables Used in Flash Addressing Variable Description PCPAGE Program Counter page address.
Although the least significant bit of the Z-register (Z0) should be zero for SPM, it should be noted that the LPM instruction addresses the Flash byte-by-byte and uses Z0 as a byte select bit. The only SPM operation that does not use the Z-pointer is setting the boot loader lock bits. The content of the Z-pointer is ignored and will have no effect on this operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations. 21.8.
21.8.5 SPM Interrupt If the SPM interrupt is enabled, it will generate a constant interrupt when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR. When using the SPM interrupt, the interrupt vectors should be moved to the boot loader section to avoid that an interrupt is accessing the RWW section when blocked for reading. Moving the interrupts is described in section “Interrupts” on page 48. 21.8.
21.10 Programming Time for Flash when Using SPM Flash access is timed using the internal, calibrated 8MHz oscillator. Typical Flash programming times for the CPU are shown in Table 84. Table 84. SPM Programming Time Operation Min (1) Max (1) SPM: Flash Page Erase, Flash Page Write, and lock bit write 3.7 ms 4.5 ms Note: 1. Min and max programming times are per individual operation. 21.11 Register Description 21.11.
z Bit 3 – RWFLB: Read/Write Fuse and Lock Bits An LPM instruction within three cycles after RWFLB and SPMEN bits are set will read either the lock bits or fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “Reading Lock, Fuse and Signature Data from Software” on page 229 for details. If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets boot lock bits and memory lock bits, according to the data in R0.
22. Lock Bits, Fuse Bits and Device Signature 22.1 Lock Bits ATtiny828 provides the program and data memory lock bits listed in Table 85. Table 85. Lock Bit Byte Lock Bit Byte Bit No Description See Default Value (1) – 7 – 1 (unprogrammed) – 6 – 1 (unprogrammed) BLB12 5 BLB11 4 1 (unprogrammed) 1 (unprogrammed) Boot lock bit Page 226 BLB02 3 1 (unprogrammed) BLB01 2 1 (unprogrammed) LB2 1 1 (unprogrammed) Lock bit LB1 0 Notes: 1.
Lock Bit Protection Modes (Application Section) Table 87. Lock Bits (1) BLB02 BLB01 1 1 No restrictions for SPM or LPM accessing the application section 1 0 SPM is not allowed to write to the application section 0 1 LPM executing from the boot loader section is not allowed to read from the application section.
Bit # Bit Name Use 3 – – 2 BOOTSZ1 See 1 (unprogrammed) 1 (unprogrammed) Sets size of boot loader section 1 BOOTSZ0 0 BOOTRST Page 216 1 (unprogrammed) Defines boot reset vector Page 216 1 (unprogrammed) Use See Default Value Page 79 1 (unprogrammed) Page 212 1 (unprogrammed) High Fuse Byte Table 90.
3. This setting selects Calibrated Internal 8MHz Oscillator. Fuse bits are locked when Lock Bit 1 (LB1) is programmed. Hence, fuse bits must be programmed before lock bits. Fuse bits are not affected by a Chip Erase. 22.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE fuse, which will take effect once it is programmed.
22.3.1 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. Signature bytes can also be read by the device firmware. See section “Reading Lock, Fuse and Signature Data from Software” on page 229. The three signature bytes reside in a separate address space called the device signature imprint table. The signature data for ATtiny828 is given in Table 93. Table 93.
See “Boot Loader Lock Bits” on page 218 for how different settings of the boot loader lock bits affect Flash access. 22.4.2 Fuse Bit Read The algorithm for reading fuse bytes is similar to the one described above for reading lock bits, only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure: 1. Load the Z-pointer with 0x0000. 2. Set RWFLB and SPMEN bits in SPMCSR. 3. Issue an LPM instruction within three clock cycles. 4.
See program example below. Assembly Code Example DSIT_read: ; Uses Z-pointer as table index ldi ZH, 0 ldi ZL, 1 ; Preload SPMCSR bits into R16, then write to SPMCSR ldi r16, (1<
23. External Programming This section describes how to program and verify Flash memory, EEPROM, lock bits, and fuse bits in ATtiny828. 23.1 Memory Parametrics Flash memory parametrics are summarised in Table 94, below. Table 94. Flash Parametrics Device Flash Size Page Size PCWORD (1) Pages PCPAGE (1) PCMSB (1) ATtiny828 4K words (8K bytes) 32 words PC[4:0] 128 PC[11:5] 11 Note: 1. See Table 96 on page 233. EEPROM parametrics are summarised in Table 95, below. Table 95.
Signals are described in Table 96, below. Pins not listed in the table are referenced by pin names. Table 96.
Table 98. XA1 and XA0 Coding XA1 XA0 Action when CLKI is Pulsed 0 0 Load Flash or EEPROM address (high or low address byte, determined by BS1) 0 1 Load data (high or low data byte for Flash, determined by BS1) 1 0 Load command 1 1 No action, idle When pulsing WR or OE, the command loaded determines the action executed. The different command options are shown in Table 99. Table 99.
5. Wait until VCC actually reaches 4.5 – 5.5V before giving any parallel programming commands. 6. Exit programming mode by powering the device down or by bringing RESET pin to 0V. 23.2.2 Considerations for Efficient Programming Loaded commands and addresses are retained in the device during programming. For efficient programming, the following should be considered.
3. Give CLKI a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte (0x00 – 0xFF). 4. Give CLKI a positive pulse. This loads the data byte. E. Latch Data 1. Set BS1 to “1”. This selects high data byte. 2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 95 for signal waveforms) F.
Figure 94. Addressing the Flash Which is Organized in Pages PCMSB PAGEMSB PROGRAM COUNTER PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Flash programming waveforms are illustrated in Figure 95, where XX means “don’t care” and letters refer to the programming steps described earlier. Figure 95. Flash Programming Waveforms F DATA A B 0x10 ADDR.
23.2.5 Programming the EEPROM The EEPROM is organized in pages, see Table 95 on page 232. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously.
z Set BS1 to “1”. The Flash word high byte can now be read at DATA z Set OE to “1” 23.2.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (see “Programming the Flash” on page 235 for details on command and address loading): z A: Load command “0000 0011” z G: Load address high byte (0x00 – 0xFF) z B: Load address low byte (0x00 – 0xFF) z Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA z Set OE to “1” 23.2.
Figure 97. Fuses Programming Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 23.2.11 Programming the Lock Bits The algorithm for programming the lock bits is as follows (see “Programming the Flash” on page 235 for details on command and data loading): z A: Load command “0010 0000” z C: Load data low byte. Bit n = “0” programs the Lock bit.
Figure 98. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte 1 BS1 BS2 23.2.13 Reading Signature Bytes The algorithm for reading the signature bytes is as follows (see “Programming the Flash” on page 235 for details on command and address loading): 1. A: Load command “0000 1000” 2. B: Load address low byte (0x00 – 0x02) 3. Set OE to “0”, and BS1 to “0”.
Figure 99. Serial Programming Signals +1.8 - 5.5V VCC +1.8 - 5.5V (2) MOSI AVCC MISO SCK CLKI (1) RESET GND Notes: 1. If the device is clocked by the internal oscillator there is no need to connect a clock source to the CLKI pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.7 – 5.5V. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation and there is no need to first execute the Chip Erase instruction.
Table 100. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PD0 I Serial Data in MISO PD1 O Serial Data out SCK PD3 I Serial Clock 23.3.2 Programming Algorithm When writing serial data to the ATtiny828, data is clocked on the rising edge of SCK. When reading data from the ATtiny828, data is clocked on the falling edge of SCK. See Figure 107 on page 257 and Figure 108 on page 257 for timing details.
6. Any memory location can be verified by using the Read instruction, which returns the content at the selected address at the serial output pin (MISO) 7. At the end of the programming session, RESET can be set high to commence normal operation 8. Power-off sequence (if required): set RESET to “1”, and turn VCC power off 23.3.3 Programming Instruction set The instruction set for serial programming is described in Table 101 and Figure 100 on page 245. Table 101.
Instruction Format Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4 Write Fuse bits (5) $AC $A0 $00 data byte in Write Fuse High bits (5) $AC $A8 $00 data byte in Write Fuse Extended Bits (5) $AC $A4 $00 data byte in Notes: 1. Not all instructions are applicable for all parts. 2. a = address. 3. Instructions accessing program memory use a word address. This address may be random within the page range. 4. Word addressing. 5.
Table 102. Typical Wait Delays Before Next Flash or EEPROM Location Can Be Written Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 3.6 ms tWD_ERASE 9.
24. Electrical Characteristics 24.1 Absolute Maximum Ratings* Operating Temperature . . . . . . . . . . . -55°C to +125°C *NOTICE: Storage Temperature . . . . . . . . . . . . . -65°C to +150°C Voltage on any Pin except RESET with respect to Ground. . . . . . . . . . -0.5V to VCC+0.5V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Symbol Parameter Condition VCC = 5V, IOH = -10 mA (4) VOH Output High-voltage Except RESET pin(6) Min (5) Typ (1) Max Units 4.3 VCC = 3V, IOH = -5 mA (5) 2.5 VCC = 1.8V, IOH = -2 mA (5) 1.4 V ILIL Input Leakage Current, I/O Pin (absolute value) VCC = 5.5V, pin low <0.05 1 µA ILIH Input Leakage Current, I/O Pin (absolute value) VCC = 5.5V, pin high <0.05 1 µA ILIAC Input Leakage Current, Analog Comparator VCC = 5V VIN = VCC/2 -50 50 nA RRST Reset Pull-up Resistor VCC = 5.
24.3 Speed The maximum operating frequency of the device is dependent on supply voltage, VCC . The relationship between supply voltage and maximum operating frequency is piecewise linear, as shown in Figure 101. Figure 101. Maximum Operating Frequency vs. Supply Voltage 20 MHz 10 MHz 4 MHz 2 MHz 1.7V 1.8V 24.4 2.7V 5.5V 4.5V Clock Characteristics 24.4.
Table 105. Calibration Accuracy of Internal 32kHz Oscillator Calibration Method Target Frequency VCC Temperature Accuracy 32kHz 1.7 – 5.5V -40°C to +85°C ±30% Factory Calibration 24.4.3 External Clock Drive Figure 102. External Clock Drive Waveform V IH1 V IL1 Table 106. External Clock Drive Characteristics VCC = 1.7 – 5.5V 24.5 VCC = 2.7–5.5V VCC = 4.5–5.5V Symbol Parameter Min. Max. Min. Max. Min. Max.
24.5.1 Power-On Reset Table 108. Symbol Characteristics of Enhanced Power-On Reset. TA = -40 to +85°C Parameter Min(1) Typ(1) Max(1) Units VPOR Release threshold of power-on reset (2) 1.1 1.4 1.6 V VPOA Activation threshold of power-on reset (3) 0.6 1.3 1.6 V SRON Power-On Slope Rate 0.01 Note: V/ms 1. Values are guidelines, only 2. Threshold where device is released from reset when voltage is rising 3.
24.7 Two-Wire Serial Interface Characteristics The following data is based on simulations and characterisations. Parameters listed in Table 111 on page 252 are not tested in production. Symbols refer to Figure 103. Table 111. Two-Wire Serial Interface Characteristics Min Max Uni t Input Low voltage -0.5 0.3 VCC V VIH Input High voltage 0.7 VCC VCC + 0.5 V VHYS Hysteresis of Schmitt-trigger inputs VOL Output Low voltage tSP Symbol Parameter VIL Condition VCC > 2.7V 0.
24.8 ADC Characteristics Table 112. Symbol ADC Characteristics. T = -40°C to +85°C. VCC = 1.7 – 5.5V Parameter Condition Min Typ Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) RAIN Units 10 Bits VREF = VCC = 4V, ADC clock = 200 kHz 2 LSB VREF = VCC = 4V, ADC clock = 1 MHz 3 LSB VREF = VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB VREF = VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
24.9 Analog Comparator Characteristics Table 113. Analog Comparator Characteristics, T = -40°C to +85°C Symbol Parameter Condition VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 Digital Propagation Delay VCC = 1.7V – 5.
Figure 105. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH CLKI BS1 PAGEL z DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 104 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 106.
Table 114. Parallel Programming Characteristics, T = 25°C, VCC = 5V Symbol Parameter Min VPP Programming Enable Voltage 11.
24.11 Serial Programming Characteristics Figure 107. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO Figure 108. Serial Programming Waveform SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 115. Symbol 1/tCLCL tCLCL Serial Programming Characteristics, T = -40°C to +85°C, VCC = 1.7 – 5.
25. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
Figure 110. Active Supply Current vs. Frequency (1 - 20 MHz) 10 5.5 V 9 5.0 V 8 4.5 V 7 ICC [mA] 6 4.0 V 5 4 3.3 V 3 2.7 V 2 1 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 111. Active Supply Current vs.
Figure 112. Active Supply Current vs. VCC (Internal Oscillator, 1 MHz) 1,2 -40 25 85 1 ICC [mA] 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 113. Active Supply Current vs.
Current Consumption in Idle Mode Figure 114. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0,14 5.5 V 0,12 5.0 V 0,1 4.5 V 4.0 V 0,06 3.3 V ICC [mA] 0,08 2.7 V 0,04 1.8 V 0,02 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency [MHz] Figure 115. Idle Supply Current vs. Frequency (1 - 20 MHz) 3 5.5 V 2,5 5.0 V 2 ICC [mA] 25.2 4.5 V 1,5 4.0 V 1 3.3 V 0,5 2.7 V 1.
Figure 116. Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz) 1,2 85 25 -40 1 ICC [mA] 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 117. Idle Supply Current vs.
Figure 118. Idle Supply Current vs. VCC (Internal Oscillator, 32kHz) 0,01 -40 25 85 0,009 0,008 0,007 ICC [mA] 0,006 0,005 0,004 0,003 0,002 0,001 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Current Consumption in Power-down Mode Figure 119. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 0,9 0,8 85 0,7 0,6 0,5 ICC [uA] 25.
Figure 120. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 6 -40 85 25 5 ICC [uA] 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Current Consumption in Reset Figure 121. Reset Current vs. Frequency (0.1 – 1MHz, Excluding Pull-Up Current) 0,12 5.5 V 0,1 5.0 V 4.5 V 0,08 ICC [mA] 25.4 4.0 V 0,06 3.3 V 0,04 2.7 V 1.
Figure 122. Reset Current vs. Frequency (1 – 20MHz, Excluding Pull-Up Current) 2,5 5.5 V 2 5.0 V 4.5 V ICC [mA] 1,5 4.0 V 1 3.3 V 0,5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 123. Reset Current vs.
Current Consumption of Peripheral Units Figure 124. Current Consumption of Peripherals at 4MHz vs. VCC 250 ADC 200 ICC [uA] 150 SPI 100 TWI USART0 T/C1 50 T/C0 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 125. Current Consumption of Peripherals at 3V vs. Frequency 500 450 ADC 400 350 300 ICC [uA] 25.
Figure 126. Watchdog Timer Current vs. VCC 0,006 -40 0,005 25 85 ICCWDT [mA] 0,004 0,003 0,002 0,001 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 127. Brownout Detector Current vs.
Figure 128. Sampled Brownout Detector Current vs. VCC 0,008 -40 0,007 85 25 0,006 ICC [mA] 0,005 0,004 0,003 0,002 0,001 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] 25.6 Pull-up Resistors 25.6.1 I/O Pins Figure 129. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.
Figure 130. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V) 80 25 85 -40 70 60 IOP [uA] 50 40 30 20 10 0 0 0,5 1 1,5 2 2,5 3 VOP [V] Figure 131. I/O pin Pull-up Resistor Current vs.
25.6.2 Reset Pin Figure 132. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 25 -40 85 35 30 IRESET [uA] 25 20 15 10 5 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET [V] Figure 133. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.
Figure 134. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 25 -40 85 100 IRESET [uA] 80 60 40 20 0 0 2 1 3 4 5 VRESET [V] 25.7 Input Thresholds 25.7.1 I/O Pins Figure 135. VIH: Input Threshold Voltage vs.
Figure 136. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘0’) 2,5 85 25 -40 Threshold [V] 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 137. VIH-VIL: Input Hysteresis vs.
25.7.2 TWI Pins Figure 138. VIH: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘1’) 3,5 85 25 -40 3 Threshold [V] 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 139. VIL: Input Threshold Voltage vs.
Figure 140. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin) 1 0,9 85 25 -40 0,8 0,7 Hysteresis [V] 0,6 0,5 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] 25.7.3 Reset Pin as I/O Figure 141. VIH: Input Threshold Voltage vs.
Figure 142. VIL: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘0’) 2,5 -40 85 25 2 Threshold [V] 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 143. VIH-VIL: Input Hysteresis vs.
25.7.4 Reset Pin Figure 144. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’) 2,5 -40 25 85 2 Threshold [V] 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 145. VIL: Input Threshold Voltage vs.
Figure 146. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin ) 1 0,8 Hysteresis [V] 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 -40 25 5,5 85 -0,2 VCC [V] 25.8 Current Source Strength 25.8.1 I/O Pins Figure 147. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.
Figure 148. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V) 3 -40 25 85 2,5 VOH [V] 2 1,5 1 0,5 0 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 149. VOH: Output Voltage vs.
25.8.2 Reset Pin as I/O Figure 150. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 1.8V 1,6 1,4 1,2 VOH [V] 1 0,8 0,6 0,4 -40 25 0,2 85 0 0 0,2 0,4 0,6 0,8 1 IOH [mA] Figure 151. VOH: Output Voltage vs.
Figure 152. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 5V 5 4 -40 25 VOH [V] 3 2 1 85 0 0,2 0 25.9 0,4 0,6 0,8 1 Current Sink Capability 25.9.1 I/O Pins with Standard Sink Capability Figure 153. VOL: Output Voltage vs. Sink Current (Standard I/O Pin, VCC = 1.
Figure 154. VOL: Output Voltage vs. Sink Current (Standard I/O Pin, VCC = 3V) 1 0,8 0,6 VOL [V] 85 25 0,4 -40 0,2 0 0 2 6 4 8 10 IOL [mA] Figure 155. VOL: Output Voltage vs.
25.9.2 I/O Pins with High Sink Capability Figure 156. VOL: Output Voltage vs. Sink Current (High Sink I/O Pin, VCC = 1.8V) 1 0,8 85 VOL [V] 0,6 25 0,4 -40 0,2 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 157. VOL: Output Voltage vs.
Figure 158. VOL: Output Voltage vs. Sink Current (High Sink I/O Pin, VCC = 5V) 1 0,8 VOL [V] 0,6 85 0,4 25 -40 0,2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] 25.9.3 I/O Pins with Extra High Sink Capability Figure 159. VOL: Output Voltage vs. Sink Current (Extra High Sink I/O Pin, VCC = 1.
Figure 160. VOL: Output Voltage vs. Sink Current (Extra High Sink I/O Pin, VCC = 3V) 1 0,8 VOL [V] 0,6 85 0,4 25 -40 0,2 0 0 5 10 15 20 IOL [mA] Figure 161. VOL: Output Voltage vs.
25.9.4 Reset Pin as I/O Figure 162. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 1.8V) 1 85 0,9 0,8 0,7 25 VOL [V] 0,6 0,5 -40 0,4 0,3 0,2 0,1 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Figure 163. VOL: Output Voltage vs.
Figure 164. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 5V) 1 85 0,8 25 0,6 VOL [V] -40 0,4 0,2 0 0 1 2 4 3 5 25.10 BOD Figure 165. BOD Threshold vs Temperature (BODLEVEL = 4.
Figure 166. BOD Threshold vs Temperature (BODLEVEL = 2.7V) 2,78 2,76 VCC RISING Threshold [V] 2,74 2,72 2,7 VCC FALLING 2,68 2,66 2,64 -60 -40 -20 0 20 40 60 80 100 Temperature [C] Figure 167. BOD Threshold vs Temperature (BODLEVEL = 1.
Figure 168. Sampled BOD Threshold vs Temperature (BODLEVEL = 4.3V) 4,36 VCC RISING VCC FALLING 4,35 Threshold [V] 4,34 4,33 4,32 4,31 4,3 4,29 -60 -40 -20 0 20 40 60 80 100 Temperature [C] Figure 169. Sampled BOD Threshold vs Temperature (BODLEVEL = 2.
Figure 170. Sampled BOD Threshold vs Temperature (BODLEVEL = 1.8V) 1,83 VCC RISING 1,825 VCC FALLING Threshold [V] 1,82 1,815 1,81 1,805 1,8 -60 -40 -20 0 20 40 60 80 100 Temperature [C] 25.11 Bandgap Voltage Figure 171. Bandgap Voltage vs.
Figure 172. Bandgap Voltage vs. Temperature (VCC = 3.3V) 1,1 5 3 1,8 Bandgap Voltage [V] 1,09 1,08 1,07 1,06 -40 -20 0 20 40 60 80 100 Temperature [°C] 25.12 Reset Figure 173.
Figure 174. Minimum Reset Pulse Width vs. VCC 3000 2500 Pulsewidth [ns] 2000 1500 1000 500 85 25 -40 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] 25.13 Analog Comparator Offset Figure 175. Analog Comparator Offset vs.
Figure 176. Analog Comparator Offset vs. VCC (VIN = 1.1V) 0,008 0,007 0,006 -40 0,005 Offset [V] 25 0,004 85 0,003 0,002 0,001 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 177. Analog Comparator Hysteresis vs. VIN (VCC = 5.
25.14 Internal Oscillator Speed 25.14.1 8MHz Oscillator with CKDIV8 Enabled Figure 178. Calibrated Oscillator Frequency vs. VCC (One-point Calibration) 1,05 -40 1,04 25 1,03 Frequency [MHz] 1,02 85 1,01 1 0,99 0,98 0,97 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC [V] Figure 179. Calibrated Oscillator Frequency vs.
Figure 180. Calibrated Oscillator Frequency vs. Temperature (One-point Calibration) 1,04 1,03 Frequency [MHz] 1,02 1,01 5.0 V 1 0,99 3.0 V 0,98 1.8 V 0,97 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°] Figure 181. Calibrated Oscillator Frequency vs. Temperature (Two-point Calibration) 1,03 1,02 1,01 Frequency [MHz] 5.0 V 1 0,99 3.0 V 0,98 1.
Figure 182. Calibrated Oscillator Frequency vs. OSCCAL0 Value 2 1,8 -40 25 85 1,6 Frequency [MHz] 1,4 1,2 1 0,8 0,6 0,4 0,2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 25.14.2 32kHz ULP Oscillator Figure 183. ULP Oscillator Frequency vs.
Figure 184. ULP Oscillator Frequency vs. Temperature 0,033 0,032 Frequency [MHz] 0,031 0,03 1.8 V 3.0 V 5.0 V 0,029 0,028 -40 -20 0 20 40 60 80 100 Temperature [°] Figure 185. ULP Oscillator Frequency vs.
26.
Address Name (0xBD) TWSD Bit 7 Bit 6 Bit 5 TWI Slave Data Register Bit 4 Bit 3 Bit 2 Bit 1 Page 211 (0xBC) TWSA TWI Slave Address Register Page 210 TWI Slave Address Mask Register Bit 0 TWAE Page(s) (0xBB) TWSAM (0xBA) TWSSRA TWDIF TWASIF TWCH TWRA TWC TWBE TWDIR TWAS Page 209 (0xB9) TWSCRB – – – – – TWAA TWCMD1 TWCMD0 Page 208 (0xB8) TWSCRA TWSHE – TWDIE TWASIE TWEN TWSIE TWPME TWSME Page 207 (0xB7) Reserved – – – – – – – – (0xB6) Reserved
Address Name (0x79) ADCH Bit 7 Bit 6 Bit 5 ADC – Conversion Result High Byte Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(s) (0x78) ADCL ADC – Conversion Result Low Byte (0x77) Reserved – – – – – – – – (0x76) Reserved – – – – – – – – (0x75) Reserved – – – – – – – – (0x74) Reserved – – – – – – – – (0x73) PCMSK3 – – – – PCINT27 PCINT26 PCINT25 PCINT24 (0x72) Reserved – – – – – – – – (0x71) Reserved – – – – – – – – (0x70) Reserved –
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(s) 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0 Page 103 0x14 (0x34) PHDE – – – – – PHDEC – – Page 81 0x13 (0x33) Reserved – – – – – – – – 0x12 (0x32) Reserved – – – – – – – – 0x11 (0x31) Reserved – – – – – – – – 0x10 (0x30) Reserved – – – – – – – – 0x0F (0x2F) PUED – – – – PUED3 PUED2 PUED1 PUED0 0x0E (0x2E) PORTD – – – – PORTD3 PORTD2 PORTD1 PORTD0
27.
Mnemonics Operands Description Operation Flags #Clocks ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
28. Ordering Information 28.1 ATtiny828 Speed (MHz) (1) Supply Voltage (V) (1) Temperature Range Package (2) Accuracy (3) Ordering Code (4) ±10% ATtiny828-AU ±2% ATtiny828R-AU ±10% ATtiny828-AUR ±2% ATtiny828R-AUR ±10% ATtiny828-MU ±2% ATtiny828R-MU ±10% ATtiny828-MUR ±2% ATtiny828R-MUR 32A 20 MHz 1.7 – 5.5V Industrial (5) (-40°C to +85°C) 32M1-A Notes: 1. For speed vs. supply voltage, see section “Speed” on page 249. 2.
29. Packaging Information 29.1 32A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) SYMBOL Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
29.2 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) K e SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 0.30 D 4.90 5.00 5.10 D1 4.70 4.75 4.80 D2 2.95 3.10 3.25 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 2.95 3.10 3.25 e Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
30. Errata The revision letters in this section refer to the revision of the corresponding ATtiny828 device. 30.1 Rev. A z Port Pin Restrictions When ULP Oscillator Is Disabled 1. Port Pin Restrictions When ULP Oscillator Is Disabled Port pin PD3 is not guaranteed to perform as a reliable input when the Ultra Low Power (ULP) oscillator is not running. In addition, the pin is pulled down internally when ULP oscillator is disabled.
31. Revision History Doc. Rev. Date 8371A 08/2012 Comments Initial document release.
ATtiny828 [DATASHEET] 8371A–AVR–08/12 308
Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. General Information . . . . . . . . . . . . . . .
9.2 9.3 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1 10.2 10.3 10.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Ports as General Digital I/O.
15.11 ADC Conversion Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.12 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.13 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 16. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.1 16.2 16.3 16.4 16.5 Features . . . . . . . . . . . . . . . . . . . . . .
21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.10 21.11 Application and Boot Loader Flash Sections. . . . . . . . . . . . . . . . . . . . . . . . . 214 Read-While-Write and No Read-While-Write Flash Sections . . . . . . . . . . . . 214 Entering the Boot Loader Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Configuring the Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Boot Loader Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 28. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 28.1 ATtiny828 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 29. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 29.1 29.2 32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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