Datasheet

24
8008HS–AVR–04/11
ATtiny48/88
– UFBGA package (32CC1) in, “Features” on page 1, “Pin Configurations” on page 2,
Section 26. “Ordering Information” on page 283, and Section 27. “Packaging
Information” on page 285
– Addresses in all Register Desc. tables, with cross-references to Register Summary
– Tape and reel in Section 26. “Ordering Information” on page 283
9.6 Rev. 8008C - 03/09
1. Updated sections:
– “Features” on page 1
– “Reset and Interrupt Handling” on page 12
– “EECR – EEPROM Control Register” on page 25
– “Features” on page 129
– “Bit Rate Generator Unit” on page 135
– “TWBR – TWI Bit Rate Register” on page 156
– “TWHSR – TWI High Speed Register” on page 160
– “Analog Comparator” on page 161
– “Overview” on page 164
– “Operation” on page 165
– “Starting a Conversion” on page 166
– “Programming the Lock Bits” on page 199
– “Absolute Maximum Ratings*” on page 206
– “DC Characteristics” on page 206
– “Speed” on page 208
– “Register Summary” on page 277
2. Added sections
– “High-Speed Two-Wire Interface Clock – clk
TWIHS
” on page 29
– “Analog Comparator Characteristics” on page 210
3. Updated Figure 6-1 on page 28.
4. Updated order codes on page 283 and page 284 to reflect changes in leadframe
composition.
9.7 Rev. 8008B - 06/08
1. Updated introduction of “I/O-Ports” on page 60.
2. Updated “DC Characteristics” on page 206.
3. Added “Typical Characteristics” on page 219.
9.8 Rev. 8008A - 06/08
1. Initial revision.