Datasheet

92
8197C–AVR–05/11
ATtiny261A/461A/861A
12.3.1.1 Prescaler Reset
Setting the PSR1 bit in TCCR1B register resets the prescaler. It is possible to use the Prescaler
Reset for synchronizing the Timer/Counter to program execution.
12.3.1.2 Prescaler Initialization for Asynchronous Mode
To change Timer/Counter1 to the asynchronous mode follow the procedure below:
1. Enable PLL.
2. Wait 100 µs for PLL to stabilize.
3. Poll the PLOCK bit until it is set.
4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.
12.4 Counter Unit
The main part of the Timer/Counter1 is the programmable bi-directional counter unit. Figure 12-
4 shows a block diagram of the counter and its surroundings.
Figure 12-4. Counter Unit Block Diagram
Signal description (internal signals):
count TCNT1 increment or decrement enable.
direction Select between increment and decrement.
clear Clear TCNT1 (set all bits to zero).
clk
Tn
Timer/Counter clock, referred to as clk
T1
in the following.
top Signalize that TCNT1 has reached maximum value.
bottom Signalize that TCNT1 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
T1
). The timer clock is generated from an synchronous system clock or an
asynchronous PLL clock using the Clock Select bits (CS1[3:0]) and the PCK Enable bit (PCKE).
When no clock source is selected (CS1[3:0] = 0) the timer is stopped. However, the TCNT1
value can be accessed by the CPU, regardless of whether clk
T1
is present or not. A CPU write
overrides (has priority over) all counter clear or count operations.
The counting sequence of the Timer/Counter1 is determined by bits WGM1[1:0], PWM1A and
PWM1B, located in the Timer/Counter1 Control Registers (TCCR1A, TCCR1C and TCCR1D).
For more details about advanced counting sequences and waveform generation, see “Modes of
Operation” on page 98. The Timer/Counter Overflow Flag (TOV1) is set according to the mode
of operation and can be used for generating a CPU interrupt.
DATA BUS
TCNT1 Control Logic
count
TOV1
top
Timer/Counter1 Count Enable
( From Prescaler )
bottom
direction
clear
PCK
CK
PCKE
clk
T1