Datasheet

90
8197C–AVR–05/11
ATtiny261A/461A/861A
back right after writing the register. The read back values are delayed for the Timer/Counter1
(TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B,
OCF1D and TOV1), because of the input and output synchronization.
The system clock frequency must be lower than half of the PCK frequency, because the syn-
chronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the
PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk
that data or control values are lost.
Figure 12-2. Timer/Counter1 Synchronization Register Block Diagram.
12.2.5 Definitions
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A, B, C or D. However, when using the register or bit
defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1
8-BIT DATABUS
OCR1A OCR1A_SI
TCNT1_SO
OCR1B OCR1B_SI
OCR1C OCR1C_SI
TCCR1A TCCR1A_SI
TCCR1B TCCR1B_SI
TCNT1 TCNT1_SI
OCF1A OCF1A_SI
OCF1B OCF1B_SI
TOV1 TOV1_SI
TOV1_SO
OCF1B_SO
OCF1A_SO
TCNT1
S
A
S
A
PCKE
CK
PCK
IO-registers Input synchronization
registers
Timer/Counter1 Output synchronization
registers
SYNC
MODE
ASYNC
MODE
1 CK Delay 1/2 CK Delay
~1/2 CK Delay 1 PCK Delay 1 PCK Delay ~1 CK Delay
TCNT1
OCF1A
OCF1B
TOV1
1/2 CK Delay 1 CK Delay
OCR1D OCR1D_SI
TC1H TC1H_SI
TCCR1C TCCR1C_SI
TCCR1D
OCF1D OCF1D_SI
OCF1D_SO
OCF1D
TC1H_SO
TC1H
TCCR1D_SI