Datasheet

85
8197C–AVR–05/11
ATtiny261A/461A/861A
11.10.4 TCNT0H – Timer/Counter0 Register High Byte
When 16-bit mode is selected (the TCW0 bit is set to one) the Timer/Counter Register TCNT0H
combined to the Timer/Counter Register TCNT0L gives direct access, both for read and write
operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes
are read and written simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers. See “Accessing Registers in 16-bit Mode” on page 79
11.10.5 OCR0A – Timer/Counter0 Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0L). A match can be used to generate an Output Compare interrupt.
In 16-bit mode the OCR0A register contains the low byte of the 16-bit Output Compare Register.
To ensure that both the high and the low bytes are written simultaneously when the CPU writes
to these registers, the access is performed using an 8-bit temporary high byte register (TEMP).
This temporary register is shared by all the other 16-bit registers. See “Accessing Registers in
16-bit Mode” on page 79.
11.10.6 OCR0B – Timer/Counter0 Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0L in 8-bit mode and TCNTH in 16-bit mode). A match can be used to gen-
erate an Output Compare interrupt.
In 16-bit mode the OCR0B register contains the high byte of the 16-bit Output Compare Regis-
ter. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing Reg-
isters in 16-bit Mode” on page 79.
11.10.7 TIMSK – Timer/Counter0 Interrupt Mask Register
• Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
Bit 76543210
0x14 (0x34) TCNT0H[7:0] TCNT0H
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x13 (0x33) OCR0A[7:0] OCR0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x12 (0x32) OCR0B[7:0] OCR0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x39 (0x59)
OCIE1D OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 TICIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R
Initial Value00000000